Elsevier

Integration

Volume 41, Issue 2, February 2008, Pages 306-316
Integration

Multi-bend bus driven floorplanning

https://doi.org/10.1016/j.vlsi.2007.09.002Get rights and content

Abstract

In this paper, the problem of bus-driven floorplanning is addressed. Given a set of blocks and bus specifications (the width of each bus and the blocks that the bus need to go through), we will generate a floorplan solution such that all the buses go through their blocks, with the area of the floorplan and the total area of the buses minimized. The approach proposed is based on a simulated annealing framework. Using the sequence pair representation, we derived and proved some necessary conditions for feasible buses, for which we allow 0-bend, one-bend, or two-bend. A checking will be performed to identify those buses that cannot be placed simultaneously. Finally, a solution will be generated giving the coordinates of the modules and the buses. Comparing with the results of the most updated work on this problem by Xiang et al. [Bus-driven floorplanning, in: Proceedings of IEEE International Conference on Computer-Aided Design, 2003, pp. 66–73], our algorithm can handle buses going through many blocks and the dead space of the floorplan obtained is also reduced. For example, if the buses have to go through more than 10 blocks, the approach in Xiang et al. [Bus-driven floorplanning, in: Proceedings of IEEE International Conference on Computer-Aided Design, 2003, pp. 66–73] is not able to generate any solution while our algorithm can still give solutions of good quality.

Introduction

Floorplanning is to plan the positions and shapes of a set of modules at the beginning of the design cycle to optimize circuit performance. Interconnect-driven floorplanning is considered to be one of the most important problems in physical design today. As the complexity of chip design increases, the amount of interconnections between different modules on a chip also increases rapidly. Bus is a collection of wires, which can be used to carry signals between different modules. Bus routing has become more and more important as the complexity of chip design increases. An area-compacted floorplan is not necessarily bus-routable. In order to ease bus routing and avoid unnecessary iterations of the physical design cycle, it would be favourable to incorporate this bus routing problem in the early designing phases. Bus-driven floorplanning considers bus placement. Buses are of different widths and need to go through different sets of modules. Therefore, the positions of the modules will affect the placement of the buses. The objective of the problem is to obtain a bus-routable floorplan such that the area of the chip and the total area of the buses are minimized.

The floorplanning problem in general is a well-studied problem. There are three kinds of floorplan: slicing, non-slicing and mosaic. Many new representations were introduced in the past decade to represent different kinds of floorplans, including sequence pair [1], bounded-sliceline grid [2], O-tree [3], B*-tree [4], transitive closure graph [5], corner block list (CBL) [6], Q-sequence [7], twin binary tree [8] and twin binary sequence [9], etc. Some of these floorplanners are extended to handle placement constraints in floorplan design. The floorplanners in [4], [10], [11] can handle pre-place constraint in which some modules are fixed in position. The paper [12], [13], [14] work on boundary constraint in which some modules are constrained to be placed along one of the four sides of the chip for I/O connection. The paper [15] generalizes the approach in [10] to handle range constraint in which some modules are restricted to be placed within some rectangular ranges. In [16], the authors tried to enforce the abutment constraint based on the CBL representation. It is shown that the abutment information of the blocks can be deduced from the CBL representation. However, the blocks on a bus are not necessarily abutted. Thus, their approach cannot be used to solve the bus driven-floorplanning problem. In [17], the authors proposed a unified method to handle simultaneously different kinds of placement constraints, including pre-placed constraint, range constraint, boundary constraint, alignment, abutment and clustering constraint, etc. All these constraints were modeled as a collection of “relative placement constraints” and “absolute placement constraints”, and were enforced by inserting edges in the constraint graphs. However, this approach is not suitable for bus-driven floorplanning as for a bus, the order in which the blocks are placed on a bus is not fixed. Besides, we do not know beforehand the shape of a bus which can be 0-bend, 1-bend, or 2-bend in our problem.

Based on the sequence pair representation, the authors of [18] proposed a method to enforce alignment constraint and some other performance constraints in floorplanning. Although the alignment constraint mentioned in [18] is not applicable for bus-driven floorplanning, their intuition on deducing the approximate positions of the blocks by looking at the sequence pair is very helpful. In [19], the authors have made use of the idea from [18] to design an intact algorithm to solve the bus-driven floorplanning problem. In [19], the authors aimed at solving the bus-driven floorplanning problem, based on a simulated annealing (SA) framework. Each candidate floorplanning solution were checked in an evaluation step to see if the buses are feasible, i.e., the required set of blocks can be passed through by a 0-bend bus. Sequence pair representation was used. One major drawback of this approach is that, only horizontal and vertical buses are considered and the solution quality will deteriorate if the number of blocks involved in each bus is large. Our proposed algorithm has made a significant improvement over [19] by allowing 0-bend, 1-bend, and 2-bend buses.

In this paper, this bus-driven floorplanning problem will be re-visited. Unlike [19], our proposed algorithm allows 0-bend, 1-bend (or 1-via), and 2-bend (or 2-via) buses. Experimental results have shown that our algorithm can generate solutions with high quality especially when the number of blocks in each bus is large. For example, if the buses have to go through more than 10 blocks each, the approach in [19] is not able to generate any solution while our algorithm can still give solutions of good quality.

The rest of this paper is organized as follows. A formal definition of the problem will be given in Section 2. After that, an algorithm is proposed to solve the problem, and details will be discussed in Section 3. Experimental results will be presented in Section 4. Finally, a conclusion will be drawn in Section 5.

Section snippets

Problem formulation

We assume that buses are routed on two layers, one for horizontal buses and the other for vertical buses. The bus-driven floorplanning problem can be formulated as follows.

Given the following:

  • (1)

    A set of n blocks B={b0,b1,,bn-1}, where each block bi is associated with a width wi and a height hi, where wi,hiR+.

  • (2)

    A set of m buses U={u0,u1,,um-1}, where each bus ui has a width ti where tiR+, and need to go through a set of blocks Bi,BiB.

Our task is to decide the position of each block and the

Methodology

SA will be used as the searching engine. A candidate solution will be evaluated according to (1) the number of buses routed successfully, (2) the total area of the buses, and (3) the total area of the floorplan. There are three main steps to evaluate a solution. The first step is to determine the shapes of the buses by examining the sequence pair. After that, a bus ordering is found such that all feasible buses can be layed out successfully by following this order. Finally, a flooplan is

Experimental results

The proposed algorithm is implemented using the C++ language and the experiments are conducted using an Intel Xeon (2.2 GHz) machine with 1 G memory. The test cases are derived from the MCNC benchmarks for floorplanning. In order to compare with the results presented in [19], the same test cases (Table 1) are tried using our proposed algorithm and all the experiments (including those of [19]) are run on the same machine. The annealing processes are implemented in such a way that the stopping

Conclusion and future work

In this paper, an algorithm to solve the bus-driven floorplanning problem allowing 0-bend, 1-bend, and 2-bend buses is proposed. Experimental results show that our approach is effective. The presence of 1-bend and 2-bend buses is important especially when the number of blocks that a bus goes through is large. It is difficult to find a solution if only 0-bend bus is allowed in those cases. One feasible extension of this work is to consider buses of other shapes with small number of vias.

Acknowledgement

We would like to thank the authors of [19] who have kindly given us their program and test cases such that we can conduct the experiments.

Jill H.Y. Law received her B.Sc. degree and M.Phil. degree in Computer Science and Engineering from The Chinese University of Hong Kong (CUHK) in 2003 and 2005, respectively.

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Jill H.Y. Law received her B.Sc. degree and M.Phil. degree in Computer Science and Engineering from The Chinese University of Hong Kong (CUHK) in 2003 and 2005, respectively.

Evangeline F.Y. Young received her B.Sc. degree and M.Phil. degree in Computer Science from The Chinese University of Hong Kong (CUHK). She received her Ph.D. degree from The University of Texas at Austin in 1999. Currently, she is an associate professor in the Department of Computer Science and Engineering in CUHK. Her research interests include algorithms and CAD of VLSI circuits. She is now working actively on floorplanning , placement and combinatorial optimization.

The work described in this paper was partially supported by a grant from the Research Grants Council of the Hong Kong Special Administrative Region, China (Project No. 4188/03E).

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