Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load

Abstract

This paper deals with the problem of estimating the performance of a CMOS gate driving RLC interconnect load. The widely accepted model for CMOS gate and interconnect line is used for the representation. The CMOS gate is modeled by an Alpha Power law model, whereas the distributed RLC interconnect is represented by an equivalent π-model. The output waveform and the propagation delay of the inverter are analytically calculated and compared with SPICE simulations. The analytical driver-interconnect load model gives sufficiently close results to SPICE simulations for two different cases of slow and fast input ramps. For each case of stimulation, the model gives an insight to four regions of operation of the CMOS gate. The voltage waveform at the end of an interconnect line is obtained for each region of operation. The SPICE and analytical results for the output voltage waveform and propagation delay match very closely.

Introduction

The performance of a high-speed chip is highly dependent on interconnects, which connect different macro cells within a VLSI chip. The feature size of integrated circuits has been aggressively reduced in the pursuit of improved speed, power, silicon area and cost characteristics [1]. Semiconductor technologies with feature sizes of several tens of nanometers are currently in development. As per International Technology Roadmap for Semiconductors [2], the future nanometer-scale circuits will contain more than a billion transistors and operate at clock speeds well over 10 GHz. Distributing robust and reliable power and ground, clock, data and address, and other control signals through interconnects in such a high-speed, high-complexity environment, is a challenging task [3]. The importance of on-chip inductance is continuously increasing with higher clock frequency, faster on-chip rise time, wider wires, ever-growing length of interconnects and introduction of new materials for low-resistance interconnects. It has become well accepted that interconnect delay dominates gate delay in current deep sub-micrometer VLSI regime. Instead of using lumped RLC model, distributed line represents more closely the behavior of actual interconnects. In current scenario, interconnect is modeled as an RLC transmission line.

Predicting accurately the waveform shape and propagation delay in a driver-interconnect load model has been an important design perspective since long time. Previously, Chatzigeorgiou et al. [4], analyzed distributed RC interconnect load represented as CRC π-model driven by CMOS gate, but inaccurately neglected inductive effects. Similarly, Dartu et al. [5], [6] started with a CRC π-model to analyze waveform and delay of an RC interconnect. Dartu et al.'s work required an empirical fitting to approximate the equivalent resistance value for modeling the CMOS gate. This empirical characterization of the gate required numerous SPICE runs for different input transition times and different load capacitances. The interconnect CRC π-circuit was mapped to an ‘effective capacitance’ that would draw the same average current during the transition period of signal. The resulting non-linear equation was solved for effective capacitance C_eff using a damped Newton–Raphson approach. After an initial guess for C_eff, number of iterations was required for converging to an appropriate C_eff. The model worked in terms of pre-characterizing the parameters of a time-varying Thevenin voltage source model (in series with a fixed resistor) over a range of effective capacitance load values. The shape of the Thevenin voltage waveshape was inaccurately modeled with a single ramp. In current DSM technology where supply voltage is highly scaled, substantial error is incurred by modeling Thevenin voltage waveform shape as linear. As supply voltage scales down, the shape of Thevenin voltage source becomes more and more non-linear and the single saturated ramp used to model this voltage source produces erroneous results. Arunachalam et al. [7] extended Dartu's work further to include RLC loading instead of RC loading but still used the same approach of inaccurately pre-characterizing gate to a linear resistance and mapping the interconnect to an effective capacitance. Dartu et al.'s work fits more in the area of library characterization for micron/sub-micron level technology, where supply voltage is not highly scaled. Our paper does not involve in pre-characterizing the gate or mapping the interconnect to an effective capacitance. We use instead a well-established model of the RLC interconnect and an alpha power law model for the transistor of CMOS gate.

Kahng and Muddu [8] proposed a π-model for distributed RLC interconnects to estimate the driving point admittance at the output of a CMOS gate. A good and simple approximation of an interconnect line is obtained with the π-model, achieving better accuracy in estimating output waveform and delay calculations. The π-model becomes more accurate as the resistance, capacitance and inductance of the distributed RLC line increases. An attempt to model the interconnect line by distributed RLC line was made in [7], [9], [10], [11], [12], [13], [14], [15], [16]; however, the driving CMOS gate was replaced by a simple resistor. In estimating the effect of inductance, when an equivalent linear resistor is used to model the non-linear CMOS transistors, leads to discrepancy in results. This linearization of the transistors results in an overestimation of the inductance effects. This behavior can be understood by noting that a transistor in a CMOS gate operates partially in the linear region and partially in the saturation region during switching. In the linear region, the transistor can be accurately approximated by a resistor. However, in the saturation region, the transistor is more accurately modeled as a current source with a parallel high resistance. The Thevenin equivalent of this circuit is a voltage source with a high resistance in series. This high resistance in series with an interconnect line over-rides the series resistance and inductance of the line. Thus, the interconnect appears predominantly capacitive (RC) when the transistor operates in the saturation region and the effect of inductance (and resistance) is negligible. Since the transistor operates partially in the saturation region, the metrics presented by all previous works represent worst case inductance effects. This paper proposes to include more accurate transistor model, i.e. Alpha power law [17], for analyzing output waveform and determining propagation delay in driver-RLC interconnect load model in a VLSI chip.

Representing transistor and distributed RLC interconnect by appropriate models results in higher accuracy. Accurate analytical expressions for the output waveform and the propagation delay is found by solving the corresponding system equations of an inverter driving a π-circuit. The parasitic capacitance due to long interconnect is large because of which the gate-to-drain coupling capacitance has negligible effect on the output. Therefore, the gate-to-drain coupling capacitance is ignored in this analysis. In brief, the equivalent π-model is used to capture with higher accuracy the performance of CMOS gates driving RLC interconnect loads. The proposed analysis determines the output waveform evolution accurately while keeping the complexity low. In addition, the output waveforms at both ends of an interconnect line are efficiently approximated by piecewise linear waveforms enabling the calculation of the voltage waveform at each point of the interconnect line. The analysis provides good results for two different cases of input ramp conditions, i.e. fast and slow.