Elsevier

Integration

Volume 37, Issue 4, September 2004, Pages 323-352
Integration

Automation of IP qualification and IP exchange

https://doi.org/10.1016/j.vlsi.2004.01.005Get rights and content

Abstract

Current and future SOC designs will use IP cores as basic building blocks. These IP cores have to fulfill defined quality characteristics. Conformance to these characteristics has to be checked automatically, as the increase in complexity makes manual checks infeasible. This article introduces IP quality aspects and describes the IP qualification platform which is able to check quality characteristics of digital soft IP. In order to distribute qualified IP it is essential to introduce an IP exchange process. More than 80% time and resource savings are expected through automated IP delivery which is based on a general IP transfer format.

Introduction

During the past decades, Moore's law has been the justification and driving force for most developments and research in the EDA industry [1], [2]. It is one of the few things which did not alter in this fast-changing environment. Moore's law is still valid. Design productivity is still growing by 21% which is far behind the increase in complexity of about 58% [3]. The latter enables the design of a whole electronic system on one single chip. Such systems are also known as system-on-a-chip (SOC). At present it is a challenge to meet time-to-market within shorter development cycles due to the productivity gap. In the future it will even be impossible to finish a design successfully without adopting new design methodologies [4].

Therefore, in the 1990s the reuse paradigm has been introduced to keep pace with Moore's law. It proposes the creation of reusable electronic designs and to use them as basic building blocks for SOC designs. Reusable designs are also called intellectual property (IP).

This paradigm ensures to meet time-to-market as it is much faster to build an SOC from pre-verified IP than to do it from scratch. Moreover, profit is increased with IP designs compared to one-time designs. The reason for this is the reusability of an IP design in different projects within the own company (intra-company reuse) but also by an external IP integrator (inter-company reuse). But reusability has to be ensured carefully by two things: market analysis and compliance with reuse characteristics. Fig. 1 shows that besides the advantages of IP driven SOC design, reuse is absolutely essential to successfully finish an SOC project [4].

In Fig. 1 the ITRS assumes a 42% improvement in design productivity which is rated as insufficient. Thereby the ITRS emanates from the basic conditions that a successful SOC design has to be finished within a time frame of 10 person years, as much new logic as possible should be integrated into an SOC design, and reused logic can be implemented twice as fast compared to new logic. Design resources for memory generation are negligible because of memory compilers. Under these circumstances SOC design is only feasible by the year 2010 when more than 80% memory cover the chip area.

Design productivity must be improved by 100%. This improvement can only be reached provided that a large percentage of reused logic is available to maximize functionality on the SOC. Fig. 2 shows that this enables an SOC design also with less than 40% of memory by the year 2016.

Since the introduction of IP based design a growing market for IP cores has been established. IP providers with specific application know-how, for example audio/video codecs or industry standard bus controllers, like PCI, develop designs which can be reused in an SOC design by an IP integrator. Often the IP integrator is a different company with competence in system design. Soon it has been realized that inter-company but also intra-company reuse is a difficult process.

Therefore, research has been done to enable and improve IP-based SOC design. IP repositories (reuse databases) are proposed in [5], [6], [7]. Ready-for-reuse IP cores are stored in an IP repository. Efficient retrieval of needed IP cores during SOC design out of a repository is focused in [8]. While other retrieval methods only rely on manually extracted characteristics, this approach allows a secured remote-simulation of an IP core model. This work enables more detailed checks on an IP core before a buy-decision has to be made. But a simulation model is not able to cover all quality aspects that are necessary for a trouble-free IP core integration.

The reuse methodology manual (RMM) [9] is an extensive collection of quality characteristics for IP cores. Its publication and acceptance among the IP community has been a great benefit because an IP provider can declare his IP core RMM compliant and an IP integrator knows which quality characteristics the IP core fulfills. OpenMORE [10] is a quality metric based on the RMM rules which enables differentiation between functional equivalent IP's according to their quality level. Adoption of RMM and OpenMORE by companies lead to better IP quality but also to additional qualification effort which mainly has to be done manually.

Focus in [5] is to integrate an IP repository in a company design-flow for efficient access from different departments within the company. This approach supports the administration and distribution of reusable IP. In [5], [6] the reuse management system (RMS) for IP retrieval is introduced. The strength of RMS is to combine the advantages of taxonomy, keywords, attributes and similarity retrieval algorithms. These approaches support an IP integrator in retrieving an existing IP core by functional characteristics. Therefore, estimating the risk included in an IP core is not possible due to missing quality information. And there is only limited support for integrating the design data into the SOC design-flow.

The previous approaches are based on functional characteristics of IP cores. In [11] RMS is extended with an object-oriented model for VHDL (objective VHDL). Support for functional modification and adaptation of IP core's content came into focus. Usually, similar but not matching IP cores have to be adapted before they can be integrated into an SOC design. While this approach allows functional adaptation of the design, adaptations of an IP core's file structure are not supported. The latter adaptation is necessary due to the migration of an IP core from IP provider's to IP integrator's design-flow.

The approach in [7] describes the definition of packages which enables the possibility to bunch dependent files together and avoids incomplete IP core deliveries. However, packages are static and do not support automatic integration into foreign design-flows.

The last paragraphs show that there are two gaps:

  • (1)

    There is no support for an efficient IP qualification. IP qualification is necessary to minimize the risk during IP integration.

  • (2)

    IP repositories are often based on version control systems like CVS, RCS, Synchronicity, Clearcase, or other proprietary formats like RMS. In order to access the IP content data within these repositories a client software or an API is necessary. Such interfaces to IP content data are not supported by most tools within the design-flow or are not available to all IP integrators. Due to this reason IP cores are delivered as plain file/directory structure. Although this structure is understood by everybody it does not support an efficient import into IP integrator's reuse database.

Contribution to the closure of these two gaps for digital soft IP is structured as follows.

There is no common agreed understanding about reusable or quality IP. The term quality has been introduced to show that IP complies with specific characteristics to ensure better reusability. But it is still unclear to an IP integrator, what he can expect from quality IP because there is no industry standard, yet. This topic is covered in Section 1.

The IP qualification platform which automatically checks compliance with IP quality characteristics, is introduced in Section 2. An implementation into a company design-flow is described in Section 3.

Due to the fact that already qualified characteristics of an IP core may get invalid during inter-company IP transfer, Section 4 proposes a quality-maintaining IP exchange process. Necessary manual tasks to maintain IP cores’ quality have to be automated for efficiency purposes and are discussed in Section 5. Details of the underlying IP content format and automatic adaptation of IP-content are described in Section 6.

Section 7 summarizes the results and Section 8 concludes this article.

Section snippets

Quality IP

Quality IP has been claimed by IP integrators when they realized that IP reuse is not that plug and play the reuse paradigm promised to be. Quality has become the keyword for good reusability. But what is quality? Quality is defined by ISO 9000 as: “the totality of features and characteristics of a product or service that bear on its ability to satisfy stated and implied needs”.

On applying this definition to quality of IP cores, it implies three things:

  • (1)

    Characteristics for reusability have to be

IP qualification platform

The IP qualification platform integrates automatic qualification checks for digital, soft IP cores. A schematic of the IP qualification platform is shown in Fig. 4. Several qualification techniques are applied to partially or completely unqualified IP cores [18]. The result of an applied subset of qualification techniques is an partially qualified IP core. All qualification techniques have to be applied for a completely qualified IP core. Not all quality characteristics can be checked

IP qualification platform implementation

During a case study, the model presented has been installed and embedded into an existing design-flow of an IP provider [20]. In the following, the three main phases, IP qualification (Section 3.1), IP certification (Section 3.2) and IP delivery (Section 3.3) are described more explicitly. Further automation of the IP delivery phase is explained in (Section 5).

IP exchange process

IP exchange implies a flow of information or data in both an IP provider and an IP integrator direction. Therefore, the term IP exchange will be used for the entire process including IP retrieval of an IP core out of a database (information flow from IP integrator to IP provider) and IP delivery (data flow from IP provider to IP integrator). IP exchange is a complex process including several tasks which have to be performed before an IP core can be integrated into an SOC design. Fig. 8 proposes

IP delivery automation

This section deals with the requirements for IP delivery automation. The IPQ format is proposed as a solution for a delivery speed-up based on the IP exchange process in Section 4. Due to the fact that IP delivery involves mainly IP content, this and the following sections will focus on the IP content after an overview of the IPQ format. Further information about IP characterization is available in [23], [25].

IP content export and import automation

Migration between tool flows will benefit from a general IP content format. The main requirement for such a format is that neither IP provider nor IP integrator have to change their internal formats, because of the previous reasons. In Fig. 10 the current manual import process is shown. This process can not be automated because it is dependent on the specific provider and integrator format. As long as files without dependencies, such as PDF documents, tool reports, or a complete VHDL directory,

Results

The IP qualification platform has been integrated into a real design-flow. The test core consists of 13 megabytes of data in 260 files and counts about 3800 gate equivalences.

The goal of this work was the development of a methodology for automated and design-flow-oriented IP quality checks, in order to fill an existing gap in the IP exchange process. The developed IP quality methodology can be mapped onto existing design-flows. For the case study, commercial tools have been customized and

Conclusion

IP reuse is necessary to finish current and future SOC designs successfully. Because reusable IP cores have to fulfill defined quality characteristics, it is necessary, on the IP provider side, to measure IP quality to detect uncovered aspects. For an IP integrator the possibility to measure IP quality reduces risk if third-party IP is integrated. Due to the fact that IP cores will become too complex to perform manual IP qualification, automated solutions have to be developed. In this article

Andreas Vörg was born in Mannheim, Germany, in 1972. In 2000 he finished his studies towards the master in Electronic Engineering at the University of Karlsruhe, Germany. His branch of study has been Technical Information Processing. Since then he has been studying towards his Ph.D. at the research group Microelectronic System Design at FZI in Karlsruhe. He has been working in the European MEDEA+ project Tools and Methods for IP (TOOLIP) and the German BMBF project Intellectual Property

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  • Cited by (5)

    Andreas Vörg was born in Mannheim, Germany, in 1972. In 2000 he finished his studies towards the master in Electronic Engineering at the University of Karlsruhe, Germany. His branch of study has been Technical Information Processing. Since then he has been studying towards his Ph.D. at the research group Microelectronic System Design at FZI in Karlsruhe. He has been working in the European MEDEA+ project Tools and Methods for IP (TOOLIP) and the German BMBF project Intellectual Property Qualification for efficient System Design (IPQ). He is active within the VSIA Virtual Component Quality Development Working Group (QDWG). His main interests are related to qualification of reusable designs, automatic checks of quality characteristics, compliance and IP transfer formats.

    Prof. Dr. Wolfgang Rosenstiel is University Professor and holds the Chair for Computer Engineering. He is also Managing Director of the Wilhelm Schickard Institute at Tbingen University and Director for the Department for System Design in Microelectronics at the Computer Science Research centre (FZI). He is also on the Executive Board of the German edacentrum. His research areas include electronic design automation, embedded systems, computer architecture, multimedia and artificial neural networks.

    This work has been partly supported by the German government under the Project IPQ (01M3048) [1] and the Medea+ project TOOLIP (A511) [2].

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