A survey on program-state retention for transiently-powered systems

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Abstract

Low-power small-scale embedded sensing systems employing batteries generally impose high maintenance costs. To enable maintenance-free operation, they are powered from energy harvested from the environment thus making them batteryless. However, due to high variance of ambient energy, these batteryless embedded devices are unable to harvest enough energy from the environment required for continuous device operation thus hampering application progress and causing frequent loss of volatile program-state. Therefore, these batteryless devices have to employ state retention mechanisms to save the volatile program-state to non-volatile storage before interruption. These batteryless embedded sensing devices are known as transiently-powered systems (TPS). In this article, we survey existing literature to identify strategies and techniques used by each existing literature to decide what amount of volatile program-state needs to be saved and when to save it. We list the challenges in retaining program-state across periods of energy unavailability and how existing state-of-the-art solutions tackle them. We also describe different memory models and discuss factors governing the choice of each model for TPS deployment.

Introduction

In recent years, the vision of “smart dust” [1] has driven the development of tiny, embedded sensing devices that run autonomously for decades. Equipped with programmable microcontroller units (MCUs), these sensing devices are envisioned to be used in large-scale applications such as wearables [2], implants [2], small satellites [3], and wireless robotic materials [4], [5]. The monitoring of existing infrastructure [6] and the environment using insects carrying the tiny devices has also been recently proposed [7], [8].

To enable these applications, the tiny sensing devices require a continuous and perpetual energy source. Batteries are commonly used to power such embedded devices [9], [10]. However, recent advances in nanotechnology and microelectronics have made it possible for these devices to shrink in size [11]; small enough to fit on the head of a honey bee [12]. Battery designs have not scaled in the same way, thus making it hard for them to fit in such devices despite recent developments [13].

Furthermore, the use of batteries nullifies the initial vision of “smart dust” of being invisible and maintenance-free. Modern-day batteries have only limited number of power cycles, i.e., batteries have one power cycle and rechargeable batteries have a few thousand. As a result, batteries from a high number of devices have to be frequently replaced, preventing a perpetual operation of the devices and resulting in high maintenance costs.

One solution to enable the maintenance-free operation of these devices is to liberate them from batteries by powering them from harvested energy [14], [15], [16], [17], e.g., from light, vibrations, and thermal sources. Miniaturized mechanical systems have enabled the design of tiny energy harvesters at the scale of nanometers that fit into the form factor of these tiny, embedded sensing devices [17], thus making them batteryless. However, the smaller an energy harvesting unit is, the smaller is the harvested energy. Furthermore, the energy that can be harvested from the environment is generally erratic and exhibits high spatial and temporal variations [17].

To cope with the small amounts of harvested energy and to smooth the fluctuations of the feeble incoming energy, devices powered by harvested energy employ an energy buffer. This is typically a capacitor offering unlimited power cycles as opposed to batteries. The form factor of this buffer must be small enough to not only fit in the device footprint but to also allow fast recharge, thus limiting its storage capacity (typically <100μF). As a result, one power cycle of this buffer cannot supply enough energy needed to complete most of the programs running on MCU.

Intermittent Program Execution. Intuitively, the notion of energy is transformed from “limited but continuous” in traditional battery-powered devices to “unrestricted but intermittent” in these maintenance-free devices. We call these tiny, energy harvesting-based, batteryless, embedded devices transiently powered systems (TPSs) and refer to the computing paradigm as intermittent computing A TPS is active when the energy buffer is full and it is inactive, i.e., it turns off, when the energy buffer is empty and is recharging. Program execution can only occur during active periods and the device loses its volatile state when the energy falls below the minimum energy that is required by the TPS to operate.

The TPS state comprises three sub-states, i.e., program-, peripheral- and timer-state, which have to be saved onto non-volatile memory (NVM) shortly before the device becomes inactive. Forward progress of the application running on the TPS can only be ensured by retaining all three sub-states at the same time. When the TPS switches back to an active period, it restores the saved system state and continues execution. However, retaining each sub-state has its challenges that are orthogonal to each other.

  • The program execution can be interrupted at any time during the operation of a TPS. At the time of interruption, size of volatile program-state is different for different applications and depends on the program-point at which energy failure occurs. Therefore, it requires sophisticated techniques to determine volatile program-state that needs to be retained across periods of energy unavailability.

  • Peripheral devices require reconfiguration after each reboot. Simply capturing the current state of these peripheral devices can result in incorrect program execution, thus giving rise to new challenges.

  • TPSs collect time-sensitive data and require time stamping of the collected data. However, transient energy supply can cause stale values to be processed by the application, thus producing incorrect results.

We discuss these challenges in detail in Section 2.1. Due to their unique set of requirements, existing literature devise different strategies to address each of the above-mentioned challenges [18], [19], [20], [21], [22], [23], [24], [25], [26].

Scope of the Survey. To keep the discussion focused, we survey existing literature to find solutions that address challenges associated with program-state retention, thus enabling energy-efficient TPS operations. This research space has seen rapid and significant progress over the past few years [18], [19], [20], [21], [22], [27], [28], [28], [29], [30], [31], [32], [33], [34], [35], [36], [37]. However, a classification and a common taxonomy in the realm of program-state retention solutions is still missing.

To this end, this paper encapsulates existing state-of-the-art solutions that answer the following research question: How to ensure the successful execution of a program on a TPS under intermittent energy supply? We build a taxonomy of solutions for program-state retention based on how they ensure forward progress of the programs running on TPSs. More precisely, this paper distinguishes between two key aspects of program-state retention. First, we discuss literature proposing strategies for reducing the energy required to retain the program-state before the TPS switches to an inactive period. Second, we focus on techniques that, based on compile-time analysis, identify program points where saving the program-state would require minimal energy.

Our Contribution. There exist well-organized surveys on energy harvesting and wireless energy transfer techniques within the sensor network domain [17], [38], [39]. There are also detailed surveys available for large-scale distributed systems regarding various checkpointing techniques [40], [41]. In contrast, we present a survey on TPSs, highlighting different checkpointing techniques and the underlying memory technologies employed by these tiny, batteryless, embedded sensing devices that have entirely different constraints than the devices used in the distributed and parallel computing domain.

A recent article surveyed several intermittent computing approaches [42] to briefly define challenges and future research directions in the TPS domain. In contrast, this paper gives a detailed survey of all existing state-of-the-art intermittent computing approaches and draws on an up-to-date taxonomy of program-state retention for TPSs. This paper covers all existing techniques, which answer the above-mentioned research question while discussing the trade-offs of different memory models on efficient program-state retention.

Organization. The rest of the paper is structured as follows. Section 2 gives the bigger picture of TPS operation while defining basic terminology and challenges faced by TPSs in retaining overall system state. Section 3 explains the criteria of classification for existing solutions for retaining program-state for TPSs. Sections 5 Trigger mechanism, 6 Checkpointing strategy classify the strategies employed by different intermittent computing solutions to ensure energy efficiency while performing program-state retention. Section 4 discusses different memory models and their trade-offs before we conclude the paper in Section 7.

Section snippets

TPS dynamics: A bigger picture

To understand the fundamental TPS operation, we consider a simple sense-compute-send application widely used in these maintenance-free devices e.g., fitness trackers [43]. The device senses value from the sensor (peripheral device) and perform computations on it (MCU) before sending the processed values to the user.

Intermittent program’s state retention: Taxonomy of solutions

In order to retain program-state across reboots, TPSs have to spend a major chunk of the energy buffer on saving the state onto NVM and reviving it; leaving a very small amount for program execution. Therefore, TPSs aim to maximize the energy spent on program execution while ensuring forward progress of the application. However, these two goals are in tension with each other.

Energy needed to perform checkpointing depends on the underlying memory model of TPS. There are three prevalent memory

TPS memory models

The transition from battery-powered to batteryless computing has brought many changes in the design, architecture and memory models of embedded computers which were previously taken for granted. In this section, we describe the modifications in memory models and discuss the trade-offs in employing each one of them.

The choice of TPS architecture to be deployed in any real-world environment is driven by the type of application and ambient energy available in the environment. Program execution and

Trigger mechanism

In the TPSs’ domain, there are two ways of deciding whether to trigger checkpointing or not, as shown in Fig. 4. We call these triggering mechanisms as Proactive and Reactive checkpointing.

Proactive. TPS inserts special function calls in the program which probes the energy buffer to decide whether it is the right time to checkpoint or not; We call these function calls as trigger calls. Note that energy failure can occur before or after these trigger calls thereby wasting the computations

Checkpointing strategy

Based on the strategy to determine checkpoint size, existing literature can be divided into two main categories; namely copy-used and copy-if-change as shown in Fig. 4.

Copy-used. This category encapsulates all those solutions which exploit the inherent division of program into different memory regions. Solutions falling under this category focus on tracking the change in size of the used memory regions and save only those regions at the time of checkpoint.

Copy-if-change. This category

Conclusion

After extensively surveying the existing state-of-art literature, we present a three-layered topological taxonomy of program-state retention solutions for TPS. First layer describes how different memory models effect the decision of what checkpoint size to save and when to trigger it. We discuss that volatile systems are a viable and an energy-efficient option for reasonably bigger capacitor size. For extremely small capacitors size, fully non-volatile system perform better. However, mixed

Declaration of Competing Interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Saad Ahmed is a Ph.D. candidate in the Department of Computer Science, School of Science and Engineering, LUMS Pakistan. His research interests include batteryless-IoT devices, embedded systems and edge computing. He has published full papers in premier venues in networked systems domain such as IPSN, EWSN and LCTES with posters in SenSys. He also worked as a visiting researcher at the Communications and Distributed Systems(ComSys) Lab, RWTH Aachen Germany for two consecutive years i.e., June

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      There has been a lot of research to alleviate these challenges through checkpointing and some hardware architecture design. Some recent surveys have been done to investigate transient computing systems [9–12]. Although both are surveys of transient computing systems, there are differences.

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    Saad Ahmed is a Ph.D. candidate in the Department of Computer Science, School of Science and Engineering, LUMS Pakistan. His research interests include batteryless-IoT devices, embedded systems and edge computing. He has published full papers in premier venues in networked systems domain such as IPSN, EWSN and LCTES with posters in SenSys. He also worked as a visiting researcher at the Communications and Distributed Systems(ComSys) Lab, RWTH Aachen Germany for two consecutive years i.e., June 2016 and July 2017. He also served as a reviewer for ICPADS and ComNets in 2019. He won the intermittent computing hackathon held at the Doctoral school organized by the IDEA league and his paper has been nominated as the Best Paper Candidate in EWSN 2020.

    Dr. Naveed Anwar Bhatti is an Assistant Professor at Air University (Pakistan). He completed his Ph.D. at Politecnico di Milano (Italy) in 2018. Later, he joined RISE (Sweden) as an ERCIM postdoctoral fellow for one and a half years. His primary research area is Cyber–Physical Systems (CPS) with a focus on transiently-powered embedded systems. Out of this research, he managed to publish papers in IPSN, EWSN, ICC, LCTES, and TOSN which are considered as flagship events in the field of networked embedded systems. He also won the best Ph.D. presentation award at IPSN 2016. He was also in the technical program committee (TPC) of ICPADS 2019, AlgoSensor 2019, ISIoT 2019 and IoTDI 2019.

    Martina Brachmann is an ERCIM Alain Bensoussan post-doctoral researcher working at the Networked Embedded Systems (NES) group of Thiemo Voigt at RISE Research Institutes of Sweden in Stockholm, Sweden. Martina’s research area is the Internet of Things with main focus on communication in low-power wireless networks. Over the past years, she has been working on different aspects and layers in the communication stack, from security over medium access control to physical layer considerations. Martina completed her Ph.D. at the Technische Universität Dresden, Germany, under guidance of Prof. Dr. Silvia Santini in 2018. From May to August 2015, she joined Prof. Dr. Olaf Landsiedel’s research group in Chalmers University of Technology, Sweden, as a research scholar. She received her Master of Science in Information and Communication Technology from the Brandenburg University of Technology Cottbus (BTU), Germany, in 2012.

    Dr. Alizai has over 10 years of experience as a researcher, software engineer, and technical lead both in industrial and academic settings. He has authored book, book chapters and published numerous scientific papers, while abroad and indigenously from Pakistan, several of them in top flight ACM SIG sponsored venues such as ACM SenSys, IPSN, BuildSYS, CoNEXT. He is experienced in leading innovative research projects in pervasive computing technologies such as Internet of things, sensor and delay tolerant networks, ICT4D, and mobile computing.  He was employed as a software engineer in several European Union projects and has a wealth of experience in teaching/training cutting edge technologies and courses in theoretical and practical computer sciences at grad, post grad and professional level. He is also a visiting researcher at his alma mater: ComSys, RWTH Aachen, Germany.

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