Experimental analysis of variability in WS 2 -based devices for hardware security

This work investigates the variability of tungsten disulfide (WS 2 )-based devices by experimental characterization in view of possible application in the field of hardware security. To this aim, a preliminary analysis was performed by measurements across voltages and temperatures on a set of seven Si/SiO 2 /WS 2 back-gated devices, also considering the effect of different stabilization conditions on their conductivity. Obtained results show appreciable variability in the conductivity, while also revealing similar dependence on bias and temperature across tested devices. Overall, our analysis demonstrates that WS 2 -based devices can be potentially exploited to ensure adequate randomness and robustness against environmental variations and then used as building blocks for hardware security primitives.


Introduction
Two-dimensional (2D) materials are widely recognized as promising technology thanks to appealing electrical, optical, and mechanical characteristics, which are attracting interest in a wide variety of fields such as transistor electronics, flexible electronics, nanophotonics, etc. [1][2][3][4][5].Taking advantage of their properties, several research groups have recently fabricated 2D materialsbased electronic devices with remarkable performance [5].However, the yield and reliability of such devices are largely affected by different types of intrinsic (vacancies, impurities, atomic misalignments, thickness fluctuation in the 2D sheet) and extrinsic (e.g., variable adhesion and interaction with the adjacent materials) defects and issues coming from the manufacturing process, also leading to large device-to-device variability [5].Although the latter typically represents an undesired effect, it can be exploited for implementing hardware security primitives leveraging stochastic process variations to generate a unique, random, and secure ID, like a fingerprint [6].Indeed, the intrinsic variability along with the mechanical flexibility of 2D materials-based devices make them particularly suitable for next-generation flexible electronics, while also targeting hardware security applications (e.g., smart labels for anticounterfeiting) [3,7].
Within the context presented above, this work focuses on the experimental characterization of variability in a set of seven back-gated devices based on tungsten disulfide (WS2), i.e., a 2D semiconducting material belonging to the transition metal dichalcogenides (TMDCs) family [8], aiming at preliminarily evaluating their suitability for hardware security primitives.More specifically, the analysis was performed with reference to a Physically Unclonable Function (PUF) bitcell implementation consisting of a voltage divider between two nominally identical series-connected devices [9,10], as shown in Fig. 1, also illustrating a typical output voltage ( ) distribution arising from M1-M2 mismatch.Indeed, this circuit leverages the devices mismatch in terms of their conductivity to generate a random voltage at the output node.At the same time, the devices must exhibit similar bias and temperature dependences to ensure adequate robustness of the PUF response against voltage and temperature variations, as well as a similar aging effect for response repeatability over time.To this aim, the variability of the conductivity of WS2-based devices was evaluated across voltages and temperatures, while also considering the effect of different stabilization conditions.
The rest of the paper is organized as follows.Section 2 details the manufacturing process and the properties of the analyzed devices.Section 3 reports and discusses measurement results at room temperature, whereas Section 4 shows the effect of temperature on device characteristics.Finally, Section 5 summarizes the main conclusions of this work.

Manufacturing process and device description
Fig. 2 illustrates the sketch of the fabricated WS2-based devices, consisting of a Si/SiO2/WS2 back-gated structure.WS2 films were directly grown on an n-type Si substrate covered by a 90-nm thick thermally grown SiO2 layer.First, a tungsten trioxide (WO3) thin film was deposited by thermal evaporation on the Si substrate at wafer level, with a deposition rate of 2.5 Å/s.The boat was filled up with WO3 powder (Aldrich 99.9) at a pressure of 8×10 -5 mbar.WS2 film synthesis was accomplished via chemical vapor deposition (CVD) through sulfurization of WO3 at a maximum temperature of 750 °C with a growth time of 20 minutes.One alumina crucible containing 0.4 g of sulfur powder (Aldrich 99.9) and pieces of silicon substrate (about 2.5cm×1.5cm)were placed in a quartz process tube (2-inch diameter).The quartz tube was then introduced into a two-temperature-zone furnace (Planartech) and the pressure was set to 10 Torr throughout the process.The tube was initially purged using argon gas (600 sccm) for 5 min at room temperature.The temperature was then increased to 150 ºC over 10 min in the WO3 stream.The argon flow was then reduced to 400 sccm and the downstream and upstream furnaces were heated to 750 ºC and 180 ºC, respectively.Subsequently, both furnaces were turned off and were naturally cooled down to 500 ºC followed by a fast cooling to room temperature in argon ambient.Finally, back-gated devices were fabricated by patterning Ni/Au metal stack as source/drain electrodes using the metal lift-off process.Isolated devices were then patterned by fluorine-based ICP dry etching process using resist as mask, which was stripped by dipping the sample in acetone.
Fig. 3 shows the micrograph of the fabricated sample along with the Atomic Force Microscopy (AFM) analysis of one typical device with channel length  = 50 µm and channel width  ≈ 1.7 µm.AFM data also show an average channel height of about 20 nm with the rms roughness of 2.68 nm (i.e., ~13%).

Measurement results at room temperature
The electrical characterization of seven devices under test (DUTs) with nominally identical dimensions ( = 50 µm and  = 1.7 µm) was performed through a Cascade SUMMIT 11861B probe station equipped with a Temptronic chuck temperature controller and a Keithley 4200-SCS parameter analyzer.The electrical characteristics were initially evaluated at room temperature ( = 25 °C).For a fair comparison, the transfer characteristics (drain current  vs gate-source voltage  ranging from +35 V to -35 V and back at drain-source voltage  = 2 V) of the different devices were measured after an initial stabilization phase, which consisted of applying  = 35 V and  = 2 V for about 470 s.To appreciate the effect of such stabilization, Fig. 4(a) reports the time evolution of  during such a phase, whereas Fig. 4(b) shows the comparison of  - curves obtained without and with stabilization for one typical device.From Fig. 4, we can observe that the stabilization at  = 35 V leads to an increased device conductivity, while also strengthening its hysteresis behavior.The latter was quantified by calculating the  shift (i.e., ∆ ) corresponding to the  value at  = 0 V during +35 V to -35 V sweep.Both effects can be mainly ascribed to charge trapping/detrapping effects due to defects near or at the oxide/channel interface [11,12].Fig. 4(b) also reveals a PMOS behavior, which can be presumably attributed to defects and vacancies in the WS2 film inducing Fermi level pinning at the interfaces with the metal contacts and the back-gate oxide [13].Both hysteresis and PMOS behaviors were consistently observed in all analyzed devices, as shown in Fig. 5     variability in terms of hysteresis (i.e.,   ⁄ = 2.4%).It is worth pointing out that in general the observed hysteretic behavior (typically depending on the level of charge trapping at the oxide/channel interface) could be detrimental for the circuit performance, especially in the case the devices belonging to the same circuit are subjected to different operating conditions.However, the very low device-to-device variability in terms of hysteresis suggests that the effects of charge trapping/detrapping mechanisms are quite consistent across analyzed devices although they exhibit rather different conductivity, thus limiting the impact of such a behavior at the circuit level.
The device-to-device variability was evaluated in more detail by measuring the output characteristics ( vs  ranging from +2 V to -2 V and back at zero- ) of DUTs, which are reported in Figs.6(a 1, such a mismatch in conductivity ensures random deviation of  from the mid-supply point.Moreover, the similar bias dependence is highly beneficial to ensure adequate robustness against voltage variations.In other words, it ensures that the strength ratio between the two devices is well-maintained across voltages. The variability of the device conductivity was also evaluated after subjecting the devices to different stabilization conditions.More specifically, for each device three different stabilization processes were applied in sequence and the output characteristics at zero- were measured at the end of each stabilization process, i.e.: (i) after an initial stabilization phase with applying  = 0 V for ~470 s, (ii) after a second stabilization phase with applying  = 35 V for ~470 s, (iii) after two further stabilization phases, i.e., the first with  = 35 V and the second with  = 0 V, both for ~470 s.Fig. 7(a) shows the corresponding  - curves related to the most conductive device among those analyzed (i.e., D2), compared to that measured without stabilization, whereas Fig. 7(b) reports the  as extracted from the  - curves measured after different stabilization processes for all devices.From Fig. 7(a), again we can observe a linear trend of  vs  regardless of the stabilization conditions.The measurements also reveal an opposite effect of the stabilization phase on the conductivity with respect to the applied voltage.Indeed, given the PMOS behavior of analyzed devices, stabilization with  = 35 V leads to an increased conductivity (as already shown in Fig. 4) owing to charge detrapping phenomena at the oxide/channel interface.On the other hand, the stabilization at  = 0 V leads to a decrease in the device conductivity likely due to charge trapping phenomena.However, such an effect is evident only in the third stabilization process, i.e., after first applying a stabilization at  = 35 V which leads to a consequent initial charge detrapping.Therefore, the slight impact of the first stabilization process at  = 0 V on the device conductivity may be ascribed to the high initial level of charge trapping in all analyzed devices.From Fig. 7(b), we can also observe that all devices reach an intermediate value of  when subjected to the third stabilization process, thus proving that the applied stabilization at  = 0 V did not allow a complete recovery of the initial conductivity.Data shown in Fig. 7(b) again denote similar behavior across devices.It is also worth noting that, although the stabilization leads to a change in the device conductivity, a similar level of variability is observed in all cases (with   ⁄ in the order of 30%).Moreover, the strength ratio between different devices is only slightly affected by the stabilization process.According to this observation, we expect the  of the PUF circuit in Fig. 1 to be not affected by the trapping state at the oxide/channel interface.

Measurements across a temperature range
The electrical characteristics of DUTs were also evaluated across a temperature range.More specifically, the analysis was performed for increasing temperatures (i.e., from 25 °C up to 100 °C with a step of 25 °C).Moreover, once the temperature was modified, a waiting time of a few hours was considered before performing - measurements given the relatively slow stabilization process in the analyzed devices.Fig. 8(a) shows the  - curves at  = 2 V and  = 100 °C for all devices, measured after an initial stabilization with applying  = 35 V for ~470 s, whereas Fig. 8(b) reports the corresponding histogram of the hysteresis-induced ∆ shift.When comparing these results with those measured at 25 °C (see Fig. 5), we can observe both increased conductivity and hysteresis at high temperatures, while again exhibiting an extremely low device-to-device variability in terms of hysteresis.
Measurements across temperatures were also performed for the output characteristics of DUTs.Figs.9(a)-(c) summarize such results referred to the  - curves measured at zero- after an initial stabilization with applying  = 0 V for about 470 s.Fig. 9(a) compares the output characteristics of the most conductive device (i.e., D2) at different temperatures.Here, we can appreciate a strong dependence of the conductivity on the temperature.In particular, the performed characterization revealed an exponential-like increase of the current with increasing temperature.Such an effect could be attributed to an increase in the carrier concentration and/or a considerable impact of the Schottky barrier junctions formed at the source and drain contacts [11,12].Also, we can presume that the major sources of the observed variability in the electrical properties of DUTs are primarily ascribed to possible variations in structural and chemical features of the WS2 film across the sample, which in turn could impact the channel resistivity as well as the potential barrier height at the metal contact/channel interfaces.The increasing trend of the conductivity for higher temperatures was consistently observed across all the devices, as given by Fig. 9(b) reporting the  (as extracted from the linear fitting of the  - curves measured at different temperatures) as a function of temperature for all analyzed devices.The same figure shows the linear fitting of the  - curves in a semilog scale, which allows effectively comparing the temperature dependence of the different devices.In this regard, Fig. 9(c) illustrates the histogram of the temperature coefficient  corresponding to the (negative) slope of the fitting lines shown in Fig. 9(b).From this figure, the analyzed devices exhibit a quite similar temperature dependence, as proven by a variability in terms of  equal to only 2.9%.Indeed, from Fig. 9(b), the relative strength ratio between different devices is quite wellmaintained across temperatures, unless the cases with very small conductivity mismatch (e.g., D1 vs. D5 and D4 vs. D6).Such outcome is again beneficial for the reference circuit shown in Fig. 1, since a similar temperature dependence across devices suggests a limited chance of flipping the PUF response under temperature variations.

Conclusion
In this work, we experimentally investigated the variability of WS2-based back-gated devices to assess their suitability for hardware security primitives such as PUFs.The electrical characteristics were evaluated across voltages and temperatures, as well as after applying different stabilization processes to the devices.Measurements demonstrated noticeable device-to-device variability in terms of conductivity (with   ⁄ in the order of 30%).The devices also exhibited comparable bias and temperature dependences, as well as similar response under different stabilization conditions.Therefore, though our analysis was performed on a limited set of seven devices, overall results preliminarily prove the potential of such a technology to be exploited for implementing PUF solutions, while ensuring adequate randomness and robustness against environmental variations.
(a) reporting the  - curve obtained after the initial stabilization for each device.Moreover, Fig. 5(b) reports the corresponding histogram of the ∆ shift as extracted from the  - curves, which shows a very low

Fig. 4 .
Fig. 4. (a) Time evolution of  during stabilization with  = 35 V and  = 2 V for about 470 s and (b)  - curves at  = 2V obtained without and with stabilization for one typical device at 25 °C.
)-(b) as obtained without any initial stabilization.Measurement results expectedly show no hysteresis in  - curves along with an almost linear trend for all devices within the considered  range.The consistent behavior of the analyzed devices across voltages is also confirmed by Fig. 6(c) showing the drain-source resistance  as a function of  .In order to quantify the variability in terms of conductivity, we extracted the  value from the linear fitting of the measured  - characteristics (i.e.,  ) for each device, as shown in Fig. 6(b).As a result of our extrapolation, Fig. 6(d) shows the  distribution with a mean value of 56.8 GΩ and a standard deviation of 16.6 GΩ, thus leading to   ⁄ = 29.2%.With reference to the circuit shown in Fig.

Fig. 6 .
Fig. 6.Output characteristics of seven devices at 25 °C and zero- without any initial stabilization: (a)  - curves, (b) detail of  - curves for  between 0 V and 2 V along with linear fitting, (c)  versus  , (d) histogram of the fitting  , i.e.,  , as extracted from the slope of linear fitting shown in (b).

Fig. 7 .
Fig. 7. Output characteristics at room temperature and zero- under different stabilization conditions: (a)  - curves of the most conductive device, i.e., D2 and (b)  for all tested devices.

Fig. 9 .
Fig. 9. (a)  - curves of the most conductive device (i.e., D2) at zero- across temperatures, as obtained after an initial stabilization with applying  = 0 V for about 470 s, (b)  versus temperature along with its linear fitting in a semilog scale across seven device, (c) histogram of the absolute value of the temperature coefficient  as extracted from the slope of the linear fitting of  - curves shown in (b).