Experimental demonstration of improved analog device performance of nanowire-TFETs

doi:10.1016/j.sse.2015.05.032

Solid-State Electronics

Volume 113, November 2015, Pages 179-183

https://doi.org/10.1016/j.sse.2015.05.032 Get rights and content

Abstract

We present experimental data on analog device performance of p-type planar- and gate all around (GAA) nanowire (NW) Tunnel-FETs (TFETs) as well as on n-type Tri-Gate-TFETs. A significant improvement of the analog performance by enhancing the electrostatics from planar TFETs to GAA-NW-TFETs with diameters of 20 nm and 10 nm is demonstrated. A maximum transconductance of 122 μS/μm and on-currents up to 23 μA/μm at a gate overdrive of V_gt = V_d = −1 V were achieved for the GAA NW-pTFETs. Furthermore, a good output current-saturation is observed leading to high intrinsic gain up to 217. The Tri-Gate nTFETs beat the fundamental MOSFET limit for the subthreshold slope of 60 mV/dec and by that also reach extremely high transconductance efficiencies up to 82 V⁻¹.

Introduction

Tunnel-FETs (TFETs) can be operated at ultralow supply voltages due to their ability to reach inverse subthreshold slopes well below 60 mV/dec [1] and their small off-state currents. Consequently, they could outperform MOSFETs in terms of energy efficiency, subthreshold characteristics and intrinsic gain, thus attracting huge interest as post CMOS-devices [2]. TFETs are not only interesting for digital applications but also for low power analog [3] and sensor applications such as ultrasensitive biomolecule and pH-detectors [4]. Up to now, experimental as well as theoretical works focused mainly on digital applications of TFETs. Only a few theoretical studies on analog and sensor application of TFETs have been published [3], [4], [5], [6], [7], [8], [9] and even less experimental data are available [10], [11]. The transconductance g_m = ∂I_d/∂V_g, output conductance g_d = ∂I_d/∂V_d and intrinsic voltage gain A_i = g_m/g_d are important figures of merit for analog circuit design. Furthermore, the transconductance efficiency g_m/I_d is a measure of analog power efficiency and is closely related to the inverse subthreshold slope SS. SS below 60 mV/dec has been experimentally demonstrated in TFETs already 10 years ago [12], however, up to now many TFET concepts suffer from low on-currents and low g_m. Continuous improvement of tunnel junctions is leading to higher on currents [13] and simulations show that TFETs can outperform MOSFETs in respect of intrinsic gain, especially due to good output current saturation (small g_d) [5]. In this work, we present experimental data on g_m, g_d, A_i as well as on the transconductance efficiency g_m/I_d of state of the art silicon based p-type planar and gate all around (GAA) nanowire (NW) TFETs as well as on tri-gate n-TFETs. The results are compared with experimental and simulation data for MOSFETs and TFETs from literature.

Section snippets

Device fabrication

In this study TFETs of two device generations have been analyzed. The devices of the first generation were symmetric doped tri-gate TFETs. The TFETs were fabricated on 15 nm thick SOI substrate by patterning with electron beam lithography followed by reactive ion etching such that 40 nm wide NWs were formed. A high-k/metal gate stack consisting of 3 nm HfO2 and 50 nm TiN was deposited by atomic layer deposition (ALD) and atomic vapor deposition AVD, respectively and patterned to a gate length of 250

Results and discussion

First, ambipolar Tri-Gate devices were investigated. These devices can operate as p- and n-type devices, as shown in the transfer characteristics in Fig. 2a.

Whereas the p-branch of these devices shows a minimum SS of 90 mV/dec. The n-branch beats the Boltzmann tyranny of 60 mV/dec. With SS_min = 29 mV/dec the n-TFET outperforms the physical limit of a MOSFET. The transconductance efficiency g_m/I_d is an important analog device performance parameter as it balances the amplification with the current

Conclusion

Experimental key-parameters for analog device application of planar, Tri-gate and GAA-NW-TFETs have been presented. Significant improvements in analog device performance by optimized device geometry going from planar technology to GAA-NWs have been demonstrated. The devices show comparable high values of intrinsic gain making them promising for low power operational amplifiers. Moreover, for TFETs they offer high g_m in combination with high on-current and good output saturation. In addition,

Acknowledgements

The research leading to these results has received funding from the European Community’s Seventh Framework Programme under grant agreement No. 619509 (project E2SWITCH) and the German BMBF project “UltraLowPower” (No. 16ES0060K).

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Experimental demonstration of improved analog device performance of nanowire-TFETs

Abstract

Introduction

Section snippets

Device fabrication

Results and discussion

Conclusion

Acknowledgements

Solid-State Electron

Solid-State Electron

Solid-State Electron

Low-voltage tunnel transistors for beyond CMOS logic

Proc IEEE

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Appl Phys Lett

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IEEE Trans Electron Dev

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Int J VLSI Des Commun Syst

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RSC Adv