Incorporation of CdSe layers into CdTe thin film solar cells

Incorporation of CdSe layers into CdTe thin film solar cells has recently emerged as a route to improve cell performance. It has been suggested that the formation of lower band gap CdTe(1-x)Se(x) phases following Se diffusion induces bandgap grading which may increase the carrier lifetime and thereby open circuit voltage. In this study we investigate the impact of CdSe incorporation on CdTe solar cell performance. We demonstrate that the standard CdS/CdTe device architecture is incompatible with Se incorporation, owing to large optical losses. An alternative cell structure with an oxide partner layer replacing the CdS with SnO2/CdSe/CdTe is developed, leading to cell efficiencies of > 13.5%. The differences in processing required for effective selenium incorporation are investigated with performance improvements resulting from additional post-growth annealing. Finally, other oxides such as TiO2, ZnO and FTO are demonstrated to be unsuitable partner layers but highlight that the choice of partner layer is key to further improving the performance.


Introduction
CdTe has established itself as the most competitive of the thin-film photovoltaics (PV) technologies currently on the market, demonstrating high performance (> 22%), long-term stability and one of the lowest costs per kWh (~0.0387 $ kWh) [1,2].
CdS was for a long time considered to be essential in achieving high performance. Cells produced without CdS (i.e. with a direct CdTe junction to the transparent conducting oxide electrode) have very low open circuit voltages (V OC ) and fill factors (FF), indicating that the CdTe/oxide interfaces were of inferior quality [3,4]. The primary benefit of CdS being that intermixing allows the formation of CdS 1-x Te x and CdTe 1-y S y phases which ease the lattice mismatch at the interface [5]. CdS is ultimately a limit to performance on account of its strong parasitic absorption in the 300-525 nm range (absorption in the CdS does not contribute to the photocurrent) [6,7]. Recent work has focused on the use of a CdSe layer to partner CdTe, either in addition to or as a replacement for CdS [2,8].
The use of a 1.7 eV band gap CdSe layer seems somewhat counterintuitive as one would anticipate the increased optical absorption in this layer would act to reduce short circuit density (J SC ) compared to CdS, if the absorptions were similarly parasitic. It has been demonstrated though that during cell processing the CdSe diffuses into the CdTe, converting it from a photoinactive CdSe (wurtzite) phase to a photoactive CdTe (1-x) Se x (zincblende) structure [4,8]. This has the effect of removing the unwanted CdSe layer, and replacing it with a lower band gap CdTe (1-x) Se (x) (≈ 1.36 eV) layer which increases photocurrent compared to CdTe. This means that in addition to a reduction in short wavelength losses [2,9], photon collection is extended to longer wavelengths. It has also been suggested that there is a bandgap grading within the CdTe (1-x) Se x layer resulting in a subsequent increase in carrier lifetime [9]. This change in the nature of the device junction via the incorporation of CdSe may make it possible to partner CdTe (1-x) Se x directly with simple oxide layers without the need for CdS. Cells produced using a CdTe (1-x) Se x structure without a CdS layer have so far shown reasonable performance, up to 14%, with the expected high current, but lower V OC and FF values [4]. Thus far however little optimisation has been carried out on what is essentially a new interface structure.
In this work we report on the development of routes to effectively incorporate CdSe layers into CdTe solar cells. The device performance of cells produced with CdSe will be compared to those with CdS and CdS/CdSe. It will be shown that use of a CdS/CdSe layer structure has severe performance limitations and that device processing conditions need to be adjusted to effectively incorporate selenium. We also demonstrate that a TCO/CdSe structure is insufficient to maintain high performance and that an interlayer, such as SnO 2 , is required between the TCO and CdSe layers, similar to the 'buffer' or 'high resistive transparent' (HRT) layer structure often used in conjunction with CdS layers [10]. Other binary oxide partner layers, ZnO and TiO 2 , are assessed for comparison to SnO 2 . We demonstrate that use of a SnO 2 in a direct junction with CdTe (1-x) Se x , and optimisation of the intermixing, allows the performance of CdS/CdTe devices to be matched. However, although this increases the J SC , concomitant V OC losses remain problematic.

Experimental
CdTe devices were produced in the conventional 'superstrate' configuration with a number of different layer structures being utilised for the readers reference devices compared in this work are shown in Fig. 1. All cells were deposited on NSG Ltd soda lime TEC™ 15 glass (F doped SnO 2 (FTO) coated glass). Unless otherwise stated 100 nm CdS was deposited via radio frequency (RF) sputtering at room temperature, using a chamber pressure of 5 mTorr (0.66 Pa) using Ar as the working gas and a power density of 1.32 W cm −2 . The base pressure reached in the sputtering chamber is 1.9 × 10 −5 Torr (2.53 mPa). Varying thicknesses of layers were also deposited by RF sputtering at room temperature using a chamber pressure of 5 mTorr using Ar as the working gas and power density of 1.32 W cm −2 .
Layers between the TCO and CdSe layer were deposited by a variety of methods: undoped SnO 2 layers (100 nm) were deposited by chemical vapour deposition (CVD) at 600°C. 100 nm of ZnO was deposited via RF sputtering at room temperature, using a chamber pressure of 5 mTorr using Ar as the working gas and a power density of 2.19 W cm −2 . 50 nm TiO 2 was deposited in a two-step process via spin-coating at 3000 rpm −1 for 30 s from titanium isopropoxide in ethanol. The first stage was the deposition of a 0.15 M solution which was then pre-annealed at 110°C for 10 min, followed by a second deposition of a 0.3 M solution which was again annealed at 110°C for 10 min. The bilayer was then heated at 550°C for 30 min in air.
Close space sublimation (CSS) was used to deposit 4-6 µm of CdTe at source and substrate temperatures of 610°C and 510°C respectively. The CdTe growth was performed in a two-stage process using: i) a 'higher pressure' growth at 30 Torr (3.99 KPa) in a nitrogen atmosphere (N 2 ) for 14 min and ii) a 'lower pressure' growth at 1 Torr (133.2 Pa) for 30 s. The growth at the higher pressure facilitates the growth of larger grains [11] while the growth at the lower pressure avoids the formation of pinholes. Specified sample were in-situ post CdTe growth annealed at 610°C in the CSS chamber at an 'elevated' pressure of 200 Torr (26.66 KPa) for a specified time, details of which are outlined as they are discussed. Use of CSS deposition can lead to a non-uniform heating of the substrate, which in turn leads to varying thicknesses in the CdTe film resulting in variations in performance.
All samples were then treated with MgCl 2 at 430°C for 20 min in an air ambient unless stated otherwise [12]. Samples were etched with a nitric -phosphoric acid (NP) solution for 15 s following the chloride activation step in order to remove contaminants and to create a Te-rich surface. In specified samples a 5 nm layer of Cu was deposited via thermal evaporation at the back surface (dark side surface) to facilitate the formation of an Ohmic contact. All cells were completed by thermally evaporating 50 nm of gold to form the back contact. All cells had an active area of 0.25 cm 2 . Current densityvoltage (JV) measurements were carried out under an AM1.5 spectrum at 1000 W m −2 using a TS Space Systems solar simulator. External quantum efficiency (EQE) measurements were performed using a Bentham PVE 300 system. For focused ion beam (FIB) milling a FEI Helios Nano Lab 600 Dual Beam system, equipped with a focused 30 keV Ga liquid metal ion source was used. Imaging was carried out using a Hitachi Su70 SEM and electron beam induced current (EBIC) analysis using a Matelect ISM5 specimen current amplifier set to a 200 nA measurement range. The beam conditions used for EBIC analysis were 8 keV with a beam current of 0.92 nA. Secondary ion mass spectrometry (SIMS) was performed using Hiden Analytical gas ion and quadrupole detector. An O 2ion gun was used to sputter the sample using a beam energy of 5 keV at a current of 300 nA, and the depth profiles were normalised. X -ray diffraction (XRD) spectra was carried out in a Rikaku © smart lab X-ray diffractometer at room temperature, using CuKα1 line as the X-ray source.

Limitations of TCO/CdS/CdSe/CdTe device structure
Initially the impact of incorporating a CdSe layer into the conventional SnO 2 /CdS/CdTe device structure (i.e. between the CdS and CdTe, see Fig. 1b) was investigated, with SnO 2 acting as the traditional HRT layer [7]. Both CdS and CdTe deposition conditions were kept the same as for our standard CdSe-free cell structure. It should be noted that for simplicity during initial process trials, Cu doping of the CdTe back surface was omitted [13][14][15]. This was done so as to isolate the influence of Se incorporation as much as possible, however this results in forward bias rollover for JV data and lower cell performance was expected [16]. Table 1 gives peak and average performance parameters extracted from JV data for cells with either a 0 nm, 50 nm or 100 nm thick CdSe layer. The JV and EQE curves for the highest efficiency contacts are shown in Fig. 2.
From this data it is clear that including the CdSe layer has a detrimental effect on performance, particularly by reducing J SC from 18.7 mA cm −2 to 15.6 mA cm −2 and FF from 61.5% to 55.1% (for 100 nm of CdSe). The progressive reduction in FF is caused by an increase in series resistance (R S ) from 7.1 Ω cm −2 to 8.6 Ω cm −2 and 12.6 Ω cm −2 with the inclusion of 0 nm, 50 nm and 100 nm CdSe layers respectively. Shunt resistance (R SH ) values are unaffected by the CdSe incorporation. EQE curves show the origin of the J SC losses: for devices that have 100 nm CdSe layers, the absorption was increased at long wavelengths, indicating the formation of a CdTe (1-x) Se x phase with a band gap of ≈ 1.38 eV. However, there were significant losses at short wavelengths, with the absorption cut-off starting to occur at ≈ 700 nm compared to ≈ 550 nm for a device with CdS only. Inclusion of CdSe has increased the wavelength range over which harmful parasitic absorption takes place. In the ideal case the CdSe should completely convert to the photoactive CdTe (1-x) Se x zincblende phase, lowering CdTe band gap and inducing band gap grading to increase carrier lifetime [9]. There are therefore two possible explanations for the observed losses either, a) the CdSe layer is still present post CSS deposition and chlorine treatments, or b) in addition to intermixing with the CdTe, the CdSe also intermixes with the CdS layer forming a CdS (1-x) Se x phase. A mixed S-Se phase would be of a lower band gap than CdS and any absorption in this layer would be parasitic [2,17]. It is notable that for a 50 nm layer of CdSe the EQE data shows a very similar short wavelength cut-off to that of the 100 nm layer, but a lesser band gap shift at long wavelengths (≈ 1.41 eV). The inference here is that for the 50 nm layer there appears to be a lower Se content in the CdTe layer, but there is the same level of parasitic absorption to the 100 nm layer. If the observed losses were due to a residual CdSe layer we would anticipate this being far more pronounced for the 100 nm layer, hence this suggests the issue is the formation of a CdS (1-x) Se x phase. Paudel et al. [4] reported no such J SC losses when CdS and CdSe were incorporated into the CdTe device structure possibly due to the differences in deposition conditions with ours favouring intermixing between the CdS and CdSe. Previous work has shown that the majority of the intermixing occurs during our CdTe deposition [5].
The nature of the short wavelength losses observed by EQE can be visualised via the use of EBIC analysis, with a high EBIC signal indicating regions of efficient carrier collection [18]. Fig. 3 shows overlaid secondary electron (red) and EBIC images (green) of device cross sections for CdS/CdTe and CdS/CdSe/CdTe. There are distinct differences in the collection for the two cells structures: The cell with no CdSe layer shows a more "typical" p-n junction response with high collection at CdS/CdTe interface and a poor collection towards the back surface of the cell [19].
In contrast the CdS/CdSe/CdTe cell shows little response at the CdS interface but collection throughout the remaining thickness of the cell. This is in accordance with EQE data presented in Fig. 2 and again suggestive of a photoinactive region, presumed to be CdS (1-x) Se x , being present at the near front surface. The presence of this unwanted interfacial layer has effectively buried the junction and is the cause of the reduced J SC observed [20]. It is worth noting that the improved deep collection could be an indication of enhanced carrier lifetime via bandgap grading [8], but that the formation of CdS (1-x) Se x phases may be a fundamental limitation of incorporating a CdSe layer when using CdS and a high temperature CdTe deposition.
In order to determine whether the CdTe layer had completely converted to the CdTe (1-X) Se X phase XRD measurements of the CdTe back surface when deposited on CdSe and CdS are shown in Fig. S1. Swanson et al. [2] demonstrated a shift to higher angles in the XRD pattern for CdTe (1-X) Se X films compared to CdTe. From this data it is clear that no shift in the XRD pattern is observed as there is very little difference between the CdTe films with both exhibiting a highly (111) orientated zincblende CdTe film. This would indicate that the Se is not diffusing though the entirety of the CdTe film, forming a continuous CdTe (1-X) Se X phase. The CdTe thickness (5-6 µm) and the interface being away from the back surface means we are unable to probe the Se content at the near interface using XRD.

Post CdTe growth annealing of CdS/CdSe/CdTe devices
The level of intermixing between CdTe and CdSe layers is liable to be controlled by two main factors, i) the CdTe deposition conditions and ii) the post-growth chloride treatment. The chloride treatment is widely associated with enhancing intermixing of the CdS and CdTe layers and improving the device performance [21]. However, it has been shown previously that for high temperature CSS-deposition the large CdTe grain structure, and subsequently the high activation energy required to recrystallize, is typically too high for intermixing to be significantly affected by the chlorine treatment. Instead the level of inter-diffusion is controlled primarily by the CdTe deposition conditions [5]. We observe a similar effect for Se diffusion, with there being little Table 1 Peak and average ± standard deviation (SD) device parameters (in brackets) showing how the incorporation of CdSe into a FTO/SnO 2 /CdS/CdTe device affects the working parameters, efficiency (η), short circuit current density (J SC ), open circuit voltage (V OC ) and fill factor (FF). CdS and CdTe thicknesses were 100 nm and 6 µm, respectively. Cell were produced without a Cu layer or post growth annealing.
CdSe thickness (nm)  notable change in device performance when increasing the MgCl 2 annealing time from 20 min to 120 min (See Fig. S2). Therefore, to enhance the amount of Se-Te inter-diffusion occurring during device fabrication, post growth annealing was performed in-situ in the CSS chamber at the growth temperature. Following completion of CdTe deposition the source temperature was maintained at 610°C, but an elevated N 2 pressure of 200 Torr was used to supress further sublimation. A series of cells were produced with such post growth annealing ranging from 0 min to 60 min Fig. 4 shows the JV and EQE responses for the highest efficiency contacts for the various annealing times, with peak and average performance parameters being given in Table 2. The post growth annealing shows some capacity to improve device performance, with all performance parameters being improved. J SC is increased from 13.1 mA cm −2 to 18.3 mA cm −2 following a 60 min anneal, with peak performance occurring following a 20 min anneal; the EQE (Fig. 4b) shows that the annealing results in some enhanced collection at short wavelengths. This improvement in J SC could be attributed to an increase in the availability of Se from the CdS (1-X) Se X which has resulted in enhanced Se-Te intermixing. It is apparent from this EQE response, that while some additional Se-Te inter-diffusion has occurred during annealing, the performance is still limited. The collection at wavelengths close to the CdTe band-edge has also been enhanced which could indicate a wider depletion region resulting from increased carrier lifetimes. Alternatively, it could indicate that a better-quality junction has been formed via recrystallisation or improved inter-diffusion at the interface. It should also be noted that the CdTe (1-x) Se x absorption cut-off doesn't change with increased annealing, which is suggestive of no significant change in the Se-Te intermixing. Whilst the average J SC improves by annealing the devices for 60 min, the overall cell performance is reduced due to a reduced FF and V OC .

Comparison of CdS and i-SnO 2 partner layers
Initial device testing strongly indicated that CdS was a limit to CdSe incorporation, potentially through the formation of a CdS (1-x) Se x phases at the interface. To test this, the CdS layer was replaced as the n-type window layer with a 100 nm undoped SnO 2 layer and a 100 nm CdSe layer (see Fig. 1c) and cells were fabricated for comparison. SnO 2 was

Table 2
Peak and average ± SD device parameters (in brackets) for CdS/CdSe (100 nm) based cells as a function of in-situ post CdTe growth annealing times at 610°C. Cells produced without a 5 nm Cu layer. chosen due to its wide band gap (4 eV) and stability thus intermixing with CdSe should be negligible [22]. Previous work has shown that use of a CdSe layer without CdS leads to the gains in J SC , but losses in both FF and V OC [4]. It was hoped that by incorporating the SnO 2 layer such losses could be minimised. All CdTe growth conditions were kept identical, including the 20 min post deposition anneal at 610°C as this was shown to produce the best device response. JV and EQE curves of the highest efficiency contacts for SnO 2 /CdSe and comparative CdS/CdSe devices are shown in Fig. 5, with extracted average and peak performance parameters given in Table 3. SnO 2 based devices yielded a slightly higher peak efficiency due to a significant improvement in J SC with peak value increasing from 18.4 mA cm −2 to 28.4 mA cm −2 . EQE analysis (Fig. 5b) of the SnO 2 /CdSe device shows a near optimal shape, with minimal losses and significantly higher collection at short wavelengths. In addition to this the EQE response has been extended to longer wavelengths, indicating higher Se incorporation into the CdTe (1-x) Se x . From this result it is clear that the CdS is indeed the limiting factor, again presumably due to the formation of CdS (1-x) Se x phases. The switch to a SnO 2 layer does however result in a drop in V OC , with peak values decreasing from 0.77 V to 0.73 V. The device FF was also impacted falling from 68.1% to 48.5%, driven primarily by an increase in R S which more than doubled from 6.6 Ω cm −2 to 13.5 Ω cm −2 . This increase in R S and drop in V OC suggests that the SnO 2 /CdTe (1-x) Se x interface is not of as high quality as the CdS/CdTe or CdS/CdTe (1-x) Se x interfaces [2]. Following the switch from a CdS to SnO 2 layer a degree of process re-optimisation was required. Device annealing post-CdTe deposition had the most impact on CdS/CdSe devices, hence this process was re-assessed for SnO 2 /CdSe based cells. Devices were annealed following CdTe deposition in the CSS chamber at 610°C for either 0 min, 20 min or 40 min, with the influence on performance being shown in Fig. 6. Associated JV and EQE curves for highest efficiency contacts are shown in Fig. 7a and b respectively. Additionally, due to the high degree of back contact related rollover observed for these devices (see Fig. 5a), 5 nm of Cu was included into the device back surface to minimise rollover and improve the FF [13]. Initial sample sets had not included Cu so the effect of Se could be investigated without being influenced by Cu. However it was expected the optimal SnO 2 /CdSe/CdTe would require Cu inclusion, hence all devices discussed from this point include Cu in the device structure.

Annealing times (min)
Devices with no post growth annealing (0 min) have low performance, with an average efficiency of only 5.5%. Annealing the devices for 20 min significantly improves the performance, with all device parameters improving and giving an average performance of 11.3%. EQE analysis (Fig. 7b) shows an improvement at short wavelengths, indicating this post-growth annealing is influencing the near interface region, and results in a J SC improvement from 21.6 mA cm −2 to 29.6 mA cm −2 . Annealing the devices for longer leads to a loss in performance with the average dropping to 9.7%, with J SC and FF dropping but V OC being maintained. The drop in FF is due to R S increasing from 5.6 Ω cm −2 to 7.9 Ω cm −2 and R SH decreasing from 727.7 Ω cm −2 to 538.7 Ω cm − 2 , this suggests that the devices have now become over treated and results in a lower performance. A range of CdSe thicknesses of 50 − 400 nm were similarly evaluated with 100 nm being found to give the highest device performance (see Supplementary Fig. S3). CdSe layers > 100 nm thick resulted in significant J SC losses via parasitic absorption. For thicker films this could be corrected partially by additional annealing (this is shown for a 200 nm film in Fig. S4 and Table  S1) but performance remained significantly lower than for 100 nm CdSe. Under these conditions it would appear there is a limit to the CdSe that can effectively be incorporated.
Poplawsky et al. [8] suggested that the CdSe wurzite phase is photoinactive whereas the CdTe (1-x) Se x zincblende structure is photoactive. We may postulate then that the unannealed samples retain some of the unconverted CdSe phase, resulting in a lower performance. Annealing has the effect of fully converting remaining CdSe to the CdTe (1-x) Se x phase. The general improvement in device performance parameters would also suggest this, as the resistive losses have decreased and the V OC has increased, indicating a more favourable interface and reduced recombination. The lower V OC for CdSe/CdTe based devices compared to CdS/CdTe, could be due simply to the CdTe (1-x) Se x phase being of a lower band gap compared to CdTe, ≈ 1.38 eV. For the case of an effectively graded bandgap and thus increased carrier lifetime we may anticipate an improved V OC . However if the bandgap of the CdTe layer has simply been uniformly reduced the maximum achievable V OC for CdTe (1-x) Se x will likewise be lowered [23].
SIMS was used to investigate the Se distribution in each sample as a function of annealing time, Fig. 8 shows normalised Se spectra for the three devices. The addition of the annealing stage has induced some Fig. 5. a) JV and b) EQE data for cells produced using SnO 2 as the n-type window rather than the conventional CdS for CdSe (100 nm)/CdTe devices. Cells were produced with a 20 min in-situ post growth anneal at 610°C and no Cu was added to the back contact. Table 3 Peak and average ± SD of device performance (in brackets) parameters for cells using CdS or SnO 2 as the device window layer in CdSe (100 nm)/CdTe devices. Cells were produced with a 20 min in-situ post growth anneal at 610°C and no Cu was added to the back contact. additional Se diffusion into the CdTe layer, with the 20 min and 40 min anneals showing higher Se content throughout the CdTe layer. The 40 min sample also shows a more uniform distribution than the 20 min anneal, however there is little suggestion of Se grading. In the ideal scenario the Se will be graded with higher content at the near interface, thus a lower bandgap, with decreasing Se content towards the back surface. Instead we see high Se content at the near interface then a reasonably linear content in the bulk. Sharp increases observed at the back surface are an artefact of the measurement, due to a change in the ion yield in the pre-equilibrium region during the early stage of the sputtering process. From the data presented it is evident that postgrowth annealing may alter the Se content in the CdTe/CdTe (1-x) Se x  however in order to achieve an ideally graded band gap some greater refinement in control of the Se diffusion may be required.

Alternatives to SnO 2 as the device window layer
In order to try and improve the V OC and FF produced by CdTe (1-x) Se x based devices different window layers were investigated as alternatives to SnO 2 . The layers compared were FTO (i.e. no additional layer), 100 nm ZnO, 50 nm TiO 2 and ultrathin (15 nm) CdS; all devices were processed identically utilising the optimal conditions shown in Section 3.3. Table 4 shows the influence of the different layers on the peak and average device parameters along with SnO 2 based devices shown for comparison. Fig. 9a and b show the JV and EQE responses produced by the highest efficiency contacts from each device.
Of the window layers compared in this study, SnO 2 based devices showed both the highest peak and average performance. Devices with an ultrathin CdS layer showed a similar average performance to SnO 2 , although peak efficiency is slightly lower. Other partner layers typically show significantly reduced performance. The CdS based devices show an enhanced average FF compared to the SnO 2 devices, 63.6% and 54.9% respectively, and improved average V OC from 0.69 V to 0.73 V, however peak V OC values are similar. The improvement in FF and V OC would seem to confirm that the CdS/CdTe (1-x) Se x interface is of a better quality than the SnO 2 /CdTe (1-x) Se x interface. However, the overall performance is reduced due to a significant reduction in device J SC , via the formation of a CdS (1-x) Se x layer, visible in EQE losses < 600 nm, even at this significantly reduced CdS thicknesses.
The devices which utilise FTO and ZnO as device window layers show a further reduction in performance due to a significant decrease in V OC with the peak dropping from 0.72 V for the SnO 2 cells to 0.66 V for both the FTO and ZnO devices respectively. This indicates that these layers are unsuited to CdTe (1-x) Se x devices, either due to a poor quality junction or low built in voltage, despite the high current that can be achieved.
TiO 2 based devices show a particularly pronounced reduction in efficiency (to an average of 5.5%) due to a low FF with an average of 30.3%. This results from the formation of an uncharacteristic Sshaped curve in the JV data at forward bias [24]. The Sshaped "kink" is not widely observed for CdTe devices but is identified as an interfacial barrier due to a misalignment of the energy bands through either an  Table 4 Peak and average ± SD device parameters (in brackets) when using ultrathin CdS, FTO, ZnO and TiO 2 as the n-type window layer. The SnO 2 based devices are also shown for comparison. Cells were in-situ post growth annealed at 610°C for 20 min and a 5 nm Cu layer was added at the back contact.   extraction or injection barrier in organic PV [22,25]. These comparative results demonstrate the importance of the correct choice of partner layer for CdSe based devices. Whilst high J SC values are obtainable with a variety of partner layers, the losses experienced in V OC and FF are controlled by the partner layer. From the development work the most suitable window structure was identified to be SnO 2 coupled to 100 nm of CdSe, with a post-growth anneal of 20 min at the growth temperature (610°C) in-situ. Here we directly compare the performance of our FTO/SnO 2 /CdSe structure with a standard FTO/SnO 2 /CdS (100 nm) structure. Table 5 gives peak and average performance parameters with JV and EQE curves for the highest efficiency contacts shown in Fig. 10a and b. The peak performance of both devices is similar being 13.5% for the CdSe device and 14.0% for the CdS. The CdSe based device shows a very high J SC of 29.6 mA cm −2 (with primary losses associated with reflection from the glass substrate and TCO) compared to 25.6 mA cm −2 when CdS is used.
The devices with CdSe have a significantly lower V OC of 0.72 V compared to 0.82 V for CdS based devices, whilst the CdS based devices also have a marginally higher FF. The loss in V OC could be due to a number of reasons: a) for the CdSe based device the band gap of the absorber layer CdTe (1-x) Se x has been lowered (≈ 1.38 eV from EQE estimation) which in turn means the maximum attainable V OC has been reduced. It should be noted that both CdSe and CdS structures show a similar voltage deficiency relative to their band gap, 52.8% and 54.6% respectively or; b) the SnO 2 /CdTe (1-x) Se x interface is of a lower quality leading to high interfacial recombination and thus a reduced V OC .

Conclusion
Through the cell led work in this paper we have identified a number of key factors related to the incorporation of CdSe layers into CdTe solar cell structures. We established that the CdS/CdSe/CdTe device structure may be fundamentally limiting due to enhanced optical losses. It is suggested that this results from the diffusion of the Se into the CdS layer, leading to the potential formation of parasitic CdS (1-x) Se x phases and hence the observed reduction in device J SC . Device current can be significantly increased by removing the CdS layer from the device structure and replacing it with a SnO 2 layer. It was found that in-situ post CdTe growth annealing was essential to achieve a high current, as it appears to modify Se diffusion into the CdTe layer i.e. it aids conversion from residual CdSe to the reportedly photoactive CdTe (1-x) Se x (zincblende) structure. Since such post growth annealing was shown to result in an improved device performance, it is necessary to further investigate the role of the post growth process to achieve finer control, as no evidence of effective Se-grading throughout the CdTe layer was observed. This served to demonstrate though that CdSe/CdTe devices require different processing approaches to those for the established CdS/CdTe device structure.
Following optimisation a SnO 2 /CdSe/CdTe cell of up 13.5% was achieved, compared to 14.0% for an equivalent SnO 2 /CdS/CdTe devices. J SC values were significantly higher for the CdSe based cell but losses occurred due to a lower V OC . However, there remains significant scope for improvement in CdSe based devices which may allow for the V OC to be increased. Initial investigations demonstrated that replacing the SnO 2 with other alternatives such as TiO 2 , ZnO and FTO led to a further reduction in the V OC , highlighting that the choice of appropriate window layer partner is essential and improving this partner layer is the route to overcoming the V OC deficit. Such improvement may involve varying the conditions of the SnO 2 deposition e.g. deposition temperature, surface treatments etc, or investigating alternative oxides (e.g. Mg x Zn (1-x) O [7,26]).
Overall this work demonstrates the feasibility of oxide/CdSe structures as a window for CdTe but that significant further work is required to establish: i) how Se diffusion can be better controlled and whether grading can be achieved; ii) whether interfacial recombination is a dominant issue with oxide partner layers; and iii) the optimal band alignment for the oxide partner layer and use this to identify feasible alternatives to CdS.