Mitigation of capacitor voltage unbalance and common mode voltage for 3-phase 5-Level NPC inverter using hexagonal SVPWM

-- Capacitor Voltage Unbalance and Common Mode Voltage (CMV) issues leads to affects the performance of the inverter, magnitude of load current increase and THD increase. So to diminish unbalance in the capacitor voltage and CMV, a hexagonal based Space Vector Pulse Width Modulation (SVPWM) is implemented for three-phase five-level Neutral Point Clamped inverter (NPCI) at high modulation index of 0.905. The performance of the inverter is improved, when the number of level of inverter increases. Simultaneously, the switching pulse creation becomes more sophisticated. SVPWM is a digital PWM control approach that maximizes the use of the dc link voltage while lowering the system's THD. And capacitor voltage (CV) imbalance and CMV are reduced by adopting the Nearest-State-Vector (NSV) technique, which selects only null, small, and large vectors and ignores medium vectors. Using Matlab Simulink and an FPGA processor, the proposes system's simulation and experimental results are established.


Introduction
In recent years, the inverter plays a momentous role in the field of industrial and variable speed drives applications [1].Even though there are a number of disadvantages, when it is used for low and high power applications [2], [3].Multilevel inverters have gotten a lot of attention lately, and they've improved their performance in terms of reduced voltage stress, lower THD, and better power quality.[4], [5].Due to attributes such as reduced CMV, reduced voltage and current harmonics, reduced switching losses and electromagnetic interference concerns, and low voltage-stresses across the switches, MLI topologies are projected as a substitute for high-power applications [6].Cascaded H-bridge, Flying capacitor, Neutral point clampediinverter, and modular MLI are the most common multilevel inverter topologies.Every topology has its own set of advantages and disadvantages [7].Among the numerous topologies available, the Neutral point clamped inverter suggests benefit such as a single dc input shared by all phases, lower THD, and less EMI [8].
The main disadvantage of NPCI [9] is the unbalance in capacitor voltage and common mode voltage.
Uneven commutation among switching devices, non-ideal dc link capacitors, non-uniform switching devices, and uneven switching pulses all contribute to increased capacitor voltage unbalance.It has an impact on the inverter's performance, increases voltage stress, rises in THD, and increases the amount of load current [10], [11].And the common mode voltage causes the motor's bearing voltage and current to rise, causing the bearing to wear out and the motor's life time is reduced.[12], [13].
Various PWM algorithms have been developed for a variety of multilevel converter topologies, which are utilized to trigger power semiconductor devices and control various converter and electric drive system characteristics [14], [15].PWM techniques such as single and multiple pulse modulation, PD, POD, APOD, hysteresis control, third harmonic elimination, and SVPWM were used for NPC-MLI [16], [17].SVPWM outperforms the others because it makes greater use of the dc input voltage, has lower harmonic levels, and uses control state variables directly to recognise switching state vectors in a complicated region.[18], [19].
In this study, a hexagonal SVPWM is used to minimize the unbalance in capacitor voltage and CMV for a five-level NPCI with a modulation index of 0.905.The hexagonal SVPWM technique is used to generate switching pulses with low THD, greater dc link voltage usage, and improved output voltage eminence.Only null, small, and large vectors are used in this system; medium vectors are not used in this process.
(it is shown in Table .1).The operation modes of 3-phase 5-level NPCI levels are depicted in Fig. 2.
✓ Phase-A produces an output voltage of +Vdc/2 V by maintaining the switches Sa1,Sa2,Sa3,Sa4 are ON and the switches Sa5,Sa6,Sa7 and Sa8 are OFF (fig.2a).For phases B and C, the stepped voltage is produced in the same manner.
✓ Switches Sa1, Sa2, Sa3, and Sa4 are turned off in phase-A, leaving OFF the switches Sa5,Sa6,Sa7 and Sa8, resulting in a Vout of -Vdc/2 V. (fig.2b).For phases B and C, the stepped voltage is produced in the same manner.✓ Phase-A produces an output voltage of -Vdc/4 V by maintaining the switches Sa4,Sa5,Sa6,Sa7 are kept ON and the switches Sa1,Sa2,Sa3,Sa8 are kept OFF (fig.2e).The output voltage is produced in a similar manner for phases B and C.

SVPWM Implementation
There are five switching modes per phase in the proposed 3-phase 5-level NPCI system (+Vdc/2, +Vdc/4, 0, -Vdc/4, -Vdc/2).The five-phase system contains a total of 125 switching modes, including 5 NVs, 60 SVs, and 30 MV and LVs, as shown in fig. 3. The redundant switching states are only achievable in SVs; all of these switching state vectors are positioned in the hexagonal region.
The control technique includes six sectors and each sector has sixteen triangles.The various switching state voltage vectors based on the NSV technique are utilised to balance the voltage across the capacitor, with large and medium state vectors being used to limit neutral point fluctuation.
The reference vectors are identified here in order to advancement the output voltage and manage the system's output current, which is distinct as: Where, V* -reference vector, δS1, δS2, and δM1 are SV1, SV2, and the MV of variousitriangles positioned in the hexagonal region.VdxT =TM3 + 0.5TM4 (7) VqxT =TM4h (8) With help of above equations, reference vector location in triangle is identified; based on this gating pulses are produced to control the NPCI.

a. Reduction of CMV
The voltage distinction between the neutral of the statorivoltage and ground is defined as the CMV.
Typically CMV level is very high in traditional 2-level VSI systems, however it can be decreased to a certain level by using MLI topology.It damages motor bearings, reduces motor life, and increases electromagnetic interference difficulties.The three phase reference voltage (Va, Vb & Vc) is converted to dq-plane (Vd & Vq) using parks transformation, which is represented by space vector modulation.The reference vector starts from origin of the hexagonal region and it ends at a certain-point, so that the length of theivector is represented as V*.
The instantaneous three phase reference vector quantity is defined as, where Va0, Vb0, Vc0 are the phase voltages of the three phase NPCI system.
In conventional two level voltage source inverter has eight switching states, in that CMV varies between +Vdc/2 to -Vdc/2 times of supplied dc source voltage.Similarly 3-phase 3-level inverter has 27 switching states, here CMV varies between +Vdc/6 to -Vdc/6 times of applied dc source voltage.But 3-phase 5level inverter has totally 125 switchingistate vectors, all these vectors are positioned in hexagonal region with 65 vertice points, where CMV varies between +Vdc/12 to -Vdc/12 times of supplied dc source voltage.The CMV ranges for 2-level, 3-level and 5-level NPCI is exposed in table.2.
The CV unbalance level is premeditated as, Similarly, the CV imbalance level is determined for VC1, VC2, VC3, and VC4 capacitors.Using the nearest three state vector selection approaches, this CV unbalance is produced by avoiding MVs.

Simulation-Results
To reduce CMV and unbalance capacitor voltage for a 3-phase 5-level NPCI, a hexagonal SVPWM control technique is simulated using Matlab Simulink.The line-to-line voltage of a three phase, five-level NPCI using SVPWM is 149.5 V, as shown in Fig. 6.According to fig. 7, the phase voltage of a three-phase, five-level NPCI using SVPWM is 100 V.As illustrated in Fig. 8, the output current of a three-phase, five-level NPCI using SVPWM is 8.3 A. Figure 11 depicts the creation of Gating pulses for phase-A using the SVPWM approach.Figure 12 depicts the harmonic investigation of the proposed three-phase 5-level NPCI system.THD investigation for output voltage is 3.12%, and THD investigation for output current is 3.69%, as shown in fig.12a and fig.12b, respectively.

Experimental Results
To authenticate the simulation results of the predicted SVPWM for 3-phase-5-level NPCI, the experimental setup is built and implemented, and the results are recognised using an FPGA processor.The switching pulse for 5-level NPCI is created using VHDL coding on the Xilinx-ISE platform.A dynamic modelling and design language for complicated analogue and digital circuits is VHDL.Fig. 13 demonstrates the control approach for the 3-phase-5-level NPCI using the SVPWM scheme.

Conclusion
In this study, a hexagonal SVPWM is implemented for a five-level NPCI to reduce the capacitor voltage and CMV imbalance while maintaining a high modulation index of 0.905.The hexagonal SVPWM technique is used to generate switching pulses with low THD, improved dc-link voltage usage, and improved output voltage quality.To lower the CMV level and capacitor voltage unbalance in the system, SVPWM selects switching state vectors using the NSV scheme, which uses only NV, MV & SV vectors.MVs are not employed during this process.
The paper's highlights are as follows:, ✓ The proposed system's CMV is dropped to 12.5 V (Vdc/12 times the supplied dc source voltage) ✓ The CVU is reduced to 0.55 percent, which is a enhanced reduction than other PWM approaches.
✓ THD of 3-phase 5-level NPCI has been diminished to 3.12% for voltage and 3.69% for current.
✓ Three-phase-five-level NPCI is developed using SVPWM with NSV scheme.

Fig. 5 .
Fig.5.Linear modulation (MI Vs NPF) The reasons for capacitor voltage unbalance are due to the non-uniform switching devices, dc-link capacitors are not in good condition, unequal commutation of switching devices.The belongings of capacitor voltage unbalance are direct to affects inverter performance, increase voltage stresses across the various switches, increases the THD in the inverter output voltage.

Table . 3
. Phase current demonstration for sector 1 Table.3 shows result assessment for various PWM methods for Capacitor voltage balancing, CMV, output voltage, and THD reduction.

Table . 3
. Result assessment for various PWM methods for Capacitor voltage balancing, CMV, output voltage, and THD reduction