A high-yield vacuum-evaporation-based R2R-compatible fabrication route for organic electronic circuits

Dyfyniad o'r fersiwn a gyhoeddwyd / Citation for published version (APA): Patchett, E. R., Patchett, E. F., Williams, A., Ding, Z., Abbas, G., Assender, H. E., Morrison, J. J., Yeates, S. G., & Taylor, D. M. (2014). A high-yield vacuum-evaporation-based R2Rcompatible fabrication route for organic electronic circuits. Organic Electronics, 15(7), 14931502. https://doi.org/10.1016/j.orgel.2014.03.043


Introduction
Over the last few years, considerable progress has been made in the design and synthesis of printable, organic semiconductors whose charge carrier mobilities are comparable with that of amorphous silicon, thus enhancing their potential for application in low-cost electronic circuitry. Examples include small molecules [1], polymers [2] and polymer/small molecule blends [3,4]. Achieving the goal of low-cost, large-area electronics, however, requires that the progress in materials development is matched by developments in manufacturing processes which are compatible with the roll-to-roll (R2R) production of, for example, printed packaging materials.
Following an early demonstration of its capability [5,6], inkjet printing was an early contender and is still under active consideration for the partial [7][8][9]  [10] fabrication of organic thin film transistors (OTFTs). In 2007 Huebler et al. [11] showed that a combination of offset, gravure and flexographic printing (a faster process than inkjet but of lower resolution) could be used to fabricate an OTFT-based 7-stage ring oscillator at a webspeed of 60 m/min. In 2010, gravure printing of batches of 50,000 OTFTs with $75% yield at 30 m/min was reported by Hambsch et al. [12]. In the same year, Voigt et al. [13] reported the gravure printing of OTFTs with modest performance at 40 m/min while Verilac et al. [14] used a combination of screen and inkjet printing to fabricate a 5-stage ring oscillator (RO). Subsequently, Noh et al. reported the gravure printing of half adder [15], full adder [16] and D-flip-flop [17] circuits fabricated entirely by gravure printing at a web speed of 10 m/min.
While the above represents significant progress towards realising low-cost electronic circuits using mass printing technologies, there are still many problems to overcome where such methods are used for all fabrication steps. Of concern is the relatively low carrier mobility, typically less than $0.04 cm 2 /V s even for small-molecule formulations [10]. This may result from the ink formulation itself, from the semiconductor morphology or from factors such as the surface roughness of (a) the gate insulator in bottom-gate or (b) the semiconductor surface in top-gate devices. When low mobility is combined with the relatively thick gate dielectric layers (typically $ 2-3 lm) and long channel lengths (typically > 40 lm) found with mass-printing methods, operating voltages in the range 50-100 V are necessary to demonstrate functioning circuits. For example, ROs typically operate at a few Hz [11,12,18], although a frequency of 300 Hz at 50 V was reported by Verilac et al. [14], for ROs fabricated on single sheets using a combination of screen and inkjet printing. Similarly, the digital circuits reported by Noh et al. [15][16][17] operated at low frequencies with stage delays >10 ms.
Although not generally considered to be a low-cost process, OTFT fabrication by vacuum thermal evaporation of the various layers has considerable attraction. Firstly, patterned metal coatings with a resolution of 30-50 lm can be applied to plastic webs, under vacuum, at web speeds of $200 m/min using a printed oil film followed by metal evaporation in a type of lift-off process [19,20]. Furthermore, thin, uniform polymer films and hybrid polymerinorganic barrier-layers may be applied to plastic sheets at high-speed in a R2R process [20][21][22]. Generally, such layers behave as electrical insulators, thus providing an established route to the deposition of, arguably, the most critical layer in any TFT fabrication process. Vacuum processing removes the need to identify orthogonal solvents and the attendant problems of drying times, handling, recovery and disposal. Other problems are also minimised such as layer interdiffusion, pinhole defects, non-uniform film thickness and surface roughness -all of which lead to device degradation and modest yield, the latter resulting in reduced production efficiency, material wastage and higher cost. When all such factors are considered, if vacuum-processing can deliver reproducible and stable transistors at high yield, it has the potential for providing an attractive route to large-area organic electronic circuit production.
We have already demonstrated that vacuum-based methods, compatible with R2R manufacture can yield OTFTs with promising performance [22][23][24][25]. We now report detailed investigations into the performance of OTFTs with dimensions compatible with high-speed, vacuum-based R2R resolution and registration capability, typically 30-50 lm and ±150 lm respectively. The consequence of this approach is that OTFT designs are not optimal. Nevertheless, an opportunity is provided for studying the influence of parasitic effects arising from such limitations which are unavoidable in high-speed R2R processes. Specifically, we report on yield, reproducibility, the dependence of field-effect mobility on channel geometry and the extraction of model parameters from output and transfer characteristics for use in circuit-simulation. We also report on progress made in fabricating and characterising inverters and ring oscillators. In particular, we apply our extracted device model for the first time to simulate inverter and RO performance and show that RO frequency could be increased by almost an order of magnitude above the observed $2 kHz by eliminating parasitic gate overlap capacitance that arises as a result of the imposed limits on registration.

Materials and methods
Substrates used for this work were pre-cleaned, 50 mm Â 50 mm squares of polyethylene naphthalate (PEN, Dupont -Teijin). Onto these substrates an 18 Â 5 array of 90 bottom-gate, top-contact OTFTs and 5 capacitors were arranged in 5 rows with channel length L increasing in steps from 50 lm to 200 lm. Each row comprised of two blocks of 9 TFTs formed on a common gate. In one of these blocks the channel width, W, was 2 mm, yielding W/L ratios ranging from 40 in the first row down to 10 in the fifth row. In the second block of 9 TFTs in each row, a constant W/L ratio of 20 was maintained so that W ranged from 1 mm in the first row to 4 mm in the fifth row. The 5 capacitors (one in each row) were arranged along a diagonal from one corner of the substrate to the other to provide a multi-point measure of the gate-insulator capacitance. Arrays of inverters and ring oscillators were prepared on other PEN substrates using the fabrication protocols developed for the OTFTs.
The gate level metallisation for both the individual OTFTs and the circuit demonstrators was achieved by thermally evaporating aluminium through appropriate Kapton shadow masks (Laser Micromachining Ltd.) onto the PEN substrates. These were then fixed onto the water-cooled drum of a R2R vacuum web coater (Aerre Machines) and rotated at a linear speed of 25 m/min. Following our previously reported procedures [22][23][24][25] tri(propyleneglycol) diacrylate (TPGDA) monomer vapour was flash-evaporated onto the metallized substrate where it condensed forming a thin liquid layer of uniform thickness which immediately passed under a plasma source where it cross-linked to form a robust insulating layer. For the present study, the substrate passed under the TPGDA nozzle several times as the drum rotated, resulting in a $500 nm thick film after 6-7 cycles. In actual R2R production, we have demonstrated that reliable dielectric films can be made by single pass deposition and curing [23]. When fabricating ring oscillators, the TPGDA was deposited through a Kapton shadow mask, the 1 mm wide gaps between rectangular islands of dielectric acting as vias for later interconnection between gate and source-drain level metallisations in the final circuit. In an eventual R2R facility such islands of dielectric could be formed by pulsing the monomer vapour supply in an additive-type process.
It is well-recognised [26] that the high-polarity surfaces associated with high dielectric constant dielectrics are detrimental to carrier mobility in OTFTs. Inevitably during the cross-linking of TPGDA, residual ester groups will be present at the insulator surface. We [25] and others [11,27] have shown that such groups may be passivated by applying a thin, non-polar buffer layer such as polystyrene (PS) to the surface prior to depositing the semiconductor. In the present case, PS (M W = 350,000; Sigma Aldrich) was spin-coated in a nitrogen glove box from a 3% solution in toluene at 1000 rpm and heated on a hot plate at 100°C for 10 min to form a buffer layer $300 nm thick. The substrates were then transferred into an integrated evaporator (Minispectros, Kurt Lesker) for the vacuum-deposition (2.4 nm/min) onto the insulator of highly pure, recrystallised dinaphtho [2,3- [28], a high-mobility, air-stable organic semiconductor [29,30]. (Although the semiconductor deposition rate is slow for a R2R process, organic vapour jet printing [31] is an additive technique that has the potential for depositing organic molecules in localised areas at far higher deposition rates and could readily be incorporated into a R2R system). After DNTT deposition and without exposing the substrates to ambient air, the gold source/ drain metallisation layer was deposited through a Kapton shadow mask in the same evaporator.
Measurements are reported on TFT arrays formed on (a) unbuffered TPGDA (substrate 1) and (b) PS-buffered TPGDA (substrates 2 and 3). Substrates 1 and 2 were manufactured in the same batch while substrate 3 was manufactured in a second batch at the same time as the substrates for the inverters and ROs.
OTFT characteristics were measured using a Keithley model 4200 Semiconductor Characterization System in ambient dark conditions. Inverter transfer characteristics were obtained using the same system. The time responses of inverters and ring oscillators were recorded by connecting the output of each circuit to a digital oscilloscope (Agilent DSO-X 2014A) via a buffer amplifier to minimise oscilloscope loading effects on the circuits.
Device parameter extraction and circuit simulations were undertaken using Silvaco's Universal Organic Thin Film Transistor (UOTFT) Model (Level = 37) and Gateway Circuit Simulator.

General observations
When tested in air immediately after fabrication, transistor transfer (I D vs V G ) characteristics were poor, see However, dramatic improvements occurred overnight with OTFT performance eventually stabilizing after $40 h. We surmise that the effect was related to oxygen take-up in the DNTT, the resultant doping increasing either the actual hole mobility [32] or the effective mobility by reducing the resistance of the bulk DNTT between contact and channel. Although no obvious change in morphology was observed, it is possible that slow, beneficial changes in crystal structure may also have occurred in the semiconductor as a result of exposing the vacuum-deposited semiconductor to atmospheric pressure in order to measure device characteristics [33]. Consequently, measurements on the 90-transistor arrays were all undertaken sequentially between 40 and 48 h after fabrication.
The capacitance of the test capacitors on the OTFT substrates varied by no more than $5% over the substrate area thus confirming the excellent thickness uniformity of the TPGDA gate dielectric produced in our process. However, there were differences between batches of insulator produced at different times. For example, for substrates 1 and 2 the average capacitance per unit area, C i , was 3.29 nF/cm 2 while for the second batch of substrates, thinner TPGDA films were targeted leading to an increase in average C i to 4.83 nF/cm 2 .
Microscope examination of the channel length, L, from a sample of devices on each substrate showed that departures from the designed value were no more than ±5 lm.

Effect of polystyrene buffer on OTFT performance
In a recent publication [25] we showed that by applying a PS buffer layer to the TPGDA, the performance of the resulting pentacene TFTs was significantly improved. Preliminary data was also given showing that a similar improvement may also be possible for DNTT devices. In this section, we provide statistical data from our 90-TFT arrays to support this earlier finding. In Fig. 2 are the linear and saturation transfer characteristics of blocks of 9 adjacent transistors with common gate (see inset of Fig. 2(a)) formed on (a) TPGDA (1 device failed) and (b) on PS-buffered TPGDA. Without buffering, strong hysteresis is observed when sweeping V G from 10 V to À60 V and back again. This, and the lack of overlap between linear and saturation characteristics in the lower current regimes, are symptomatic of an unstable threshold voltage. Nevertheless, turn-on voltages are in the range ±10 V and even though off-currents are relatively high, especially in saturation, on-off ratios are $10 5 .
In contrast, the off-currents of the PS-TPGDA devices in the linear regime are below the noise floor of our measurement system ($1 pA) and increase to only $10 pA in saturation, leading to on-off ratios in excess of 10 6 . Some of these devices displayed a shallower subthreshold slope at low currents, probably arising from a higher interface trap density [34]. However, no hysteresis was observed between the forward and reverse voltage sweeps, as evidenced by the transfer characteristics in Fig. 3 of one of the devices from Fig. 2(b). In almost all PS-buffered devices the gate leakage current, I G , was independent of sourcedrain voltage, V D , but greater than the off-current, suggesting that gate-source leakage dominated gate current.
Device current, I D , in the linear regime is given by and in saturation by where V T is the threshold voltage. The mobilities in the linear (l lin ) and saturation (l sat ) regimes were extracted from the local slopes of the transfer plots using, respectively, the equations [35] l lin ¼ and It should be noted, though, that these equations are only valid when the mobility is weakly dependent on gate voltage and can lead to an over-estimate when mobility increases strongly with V G while under-estimating when mobility decreases with V G [36].
With this caveat, extracted mobilities from the transfer characteristics in Fig. 3 are plotted as a function of V G in the figure inset. Both l lin and l sat begin to increase rapidly at about À7 V following similar paths. As V G becomes more negative, l lin rises more rapidly, eventually reaching a maximum of 1.29 cm 2 /V s before decreasing to 1.24 cm 2 /V s  when V G = À40 V. This slight decrease may be real and caused by carrier scattering at the higher gate voltages. However, such an effect is thought to occur at much higher channel carrier densities (>10 13 cm À2 ) [36] than is the case here ($10 12 cm À2 ). A second possibility is the presence of contact/series resistances at the source and drain. By reducing the effective potentials experienced by the accumulation channel, I D and hence the extracted mobility are lower than expected for the given applied voltage conditions [37]. Unexpectedly, after lagging behind initially, l sat increased above l lin and continued to increase for increasingly negative V G . (c) For PS-TPGDA devices with constant W/L = 20, l lin and l sat increase on average by $50% and $30% respectively as L decreases from 200 lm to 50 lm (W decreasing from 4 mm to 1 mm). This effect is readily explained by the increased area in which a parasitic source-drain fringe current can flow between the tip of one electrode and its counterelectrode (see insets in Fig. 2). As W decreases, the parasitic current then provides a greater fraction of the total device current. The larger values of l sat in the PS-TPGDA devices suggest that the higher source-drain voltage, V D = À40 V, applied during these measurements causes the fringe currents to increase even after the main channel has saturated.
Although not shown here, this is reflected in the saturation region of the output characteristics, which display a finite and decreasing output resistance (increasing slope) as W and L decrease to lower values. Similar trends were observed in TPGDA-only devices and are responsible for the high mobility tails in the distributions in Fig. 4(a). However, the similar values for l lin and l sat suggest that parasitic currents in these devices are less sensitive to V D . This probably reflects the lower mobility and/or poorer turn-on characteristics in these devices, which in turn results in a weaker V G -dependence of the DNTT sheet conductance in the regions outside the main channel.
(d) For devices in which W = 2 mm, both l lin and l sat increase by $18% as L decreases from 200 lm to 50 lm. Since the area in which parasitic currents can flow are identical in all these devices, then the relative contribution of the parasitic fringe currents must also increase slowly as L decreases. (e) Mobilities extracted for the two devices from the second batch of PS-TPGDA substrates (open circles in Fig. 4(c)) fit well with the pattern observed for devices from the first batch confirming the reproducibility of the fabrication process even using thinner PS-TPGDA films. (f) Detailed analysis of the spatial distribution over the substrate area of the mobility values in Fig. 4(b) and (c) indicated a systematic decrease towards the middle of the substrate suggesting the presence of a process-dependent parameter. Since we did not measure insulator thickness and insulator capacitance for every device on the substrate, it is possible that changes in dimensions may be responsible. However, the small variations found in the test capacitors (see above) and observed departures from the designed channel length would be insufficient to explain the mobility differences observed. Other possibilities include differences in DNTT thickness and/or morphology leading to changes in mobility either directly or indirectly e.g. through the effects of parasitic series resistance between the contacts and the active channel.
From the above considerations, we deduce, therefore, that the true hole mobility in our TFTs is likely to be $1 cm 2 /V s. This being the case, it is clear that parasitic source-drain currents can inflate l lin by $40% and l sat by $80% when channel dimensions, especially W, are small relative to the gate and semiconductor dimensions. Clearly, careful device design will reduce such effects. However, while achieving the ideal structure (self aligned gates and appropriately patterned semiconductor) is possible for low-speed, small batch production, this is unlikely in a high speed R2R process until significant advances are made in web control.

Extraction of OTFT parameters
In a recent publication [24] we showed that the Silvaco UOTFT parameter extraction software was effective in allowing relevant device parameters to be extracted. That work was mainly concerned with TPGDA-based devices with one example given for a PS-TPGDA/DNTT transistor measured under vacuum. Here we use the same software to extract parameters for PS-TPGDA/DNTT devices measured in air. The model card thus extracted was then used for the first time to simulate the performance of circuits assembled using our TFT fabrication protocols. Based on the discussion in the previous section, the two devices represented by the open circles in Fig. 4 were considered the most likely to provide representative device parameters since they are the least affected by parasitic currents. In Fig. 5, therefore, we show the results of simulating both the transfer and output characteristics of these two adjacent devices (L = 200 lm, W = 2 mm) fabricated on the second batch of PS-TPGDA substrates.
As can be seen, the characteristics of both devices follow each other closely confirming the reproducibility of adjacent devices. Not surprisingly, they can also be simulated accurately with only minor changes in device parameters (see Table 1). It should be noted that the linear and saturation regimes of the output and transfer plots were fitted simultaneously thus testifying to the electrical stability of the devices.
Some of the parameter values extracted here are close to those published earlier for device O-D04 [24]. In particular l ACC , the mobility at the onset of strong channel accumulation, is $1 cm 2 /V s and very close to the maximum linear mobility extracted using Eq. (3). The gatevoltage dependence of mobility represented by the power-law parameter, c, is weak in buffered devices ranging from 0 to 0.03 compared with 0.3 for the unbuffered device, B-D12. In all cases good saturation of the output characteristics was observed, k = 0. The output characteristic shape parameters, M SAT (the knee-shape parameter) and A SAT (a parameter that modulates the voltage corresponding to the onset of saturation) were similar in all cases. This good agreement between the different PS-buffered devices again confirms the reproducibility of device production -device O-D04 was fabricated at a different time and in a different laboratory to the two devices reported here. Where significant differences in fitting parameters do occur, these we may attribute to the fact that, although previously exposed to air for some time, device O-D04 was actually measured under vacuum. The non-zero source/drain series resistances R S and R D extracted in this case supports the argument that the improved device performance observed in the 2 days after fabrication (Fig. 1) is, at least partially, the result of airdoping. Furthermore, the threshold voltage, V T , and the density of states parameter, V 0 , are both lower in the device measured under vacuum, again suggesting that atmospheric air or moisture influences both the insulator and the insulator/semiconductor interface.  Table 1.

PS-TPGDA/DNTT inverter
Using PS-buffered TPGDA as the gate insulator and a similar transistor design to that in Fig. 2, batches of 27 unipolar, saturated-load inverters (inset Fig. 6) were fabricated on each of 10 substrates (2nd batch of PS-TPGDA) with a 100% yield being achieved. The W/L ratios for the driver and load transistors were (2500 lm)/(50 lm) and (625 lm)/(100 lm) respectively. The inset in Fig. 6 demonstrates the inverter response to a slowly varying square wave and confirms stable device operation. The main figure shows the experimentally obtained voltage transfer characteristics for the device (points) for different supply voltages (V DD ). For comparison we also give the simulated response (lines) based on the model card in Table 1 for Device 1 but with the appropriate values for W and L substituted for the driver and load transistors.
The simulated plots obtained using Silvaco's Gateway SPICE-modeller, provide a reasonable match to the experimental results over much of the operational range. However, they clearly underestimate the 'pull-up' ability of the load transistor. This is not surprising given the effect of device geometry on the saturation mobility in Fig. 4(c). While the relative magnitude of the parasitic source-drain current effect will be small in the driver transistor (W = 2.5 mm) compared to Device 1 (W = 2 mm), it will be much greater in the saturated load transistor (W = 0.625 mm). To achieve improved simulations, therefore, it would be necessary to include in the TFT model a description of the additional V D -dependent parasitic source-drain current depicted in Fig. 2(b). Alternatively, the simulation could be validated in additional experiments in which the semiconductor is appropriately patterned as discussed earlier.

PS-TPGDA/DNTT ring oscillators
Using the same high-yield fabrication protocols established for the TFTs and inverters, both 5-and 7-stage ring oscillators (ROs) were fabricated, again on the 2nd batch of PS-TPGDA substrates. As shown in the inset of Fig. 8, the ROs were based on inverters composed of a driver transistor, W/L = (4000 lm)/(50 lm), and a saturated transistor load, W/L = (400 lm)/(50 lm). Measurements on the 7stage device were commenced some 21 h after the final fabrication step i.e. during the period when transistor performance was close to, but not in, the stable range following the initial increase (Fig. 1). The 5-stage device was kept in a sealed, translucent plastic box under laboratory conditions for 1 month prior to measurements. For both cases, the devices began to generate an output signal >100 Hz even with V DD as low as À15 V (Fig. 7). On increasing V DD , device frequencies increased non-linearly. With V DD = À90 V the 5-stage RO achieved an output frequency Table 1 Fitting parameters for DNTT devices with different gate dielectrics. The parameters are described in the text except for r 0 the minimum bulk conductance. It was assumed in all the simulations that, the characteristic voltage of the effective mobility, V ACC = 1 and the leakage saturation current, I OL = 3 fA. The parameters for devices B-D12 and O-D04 were reported previously [24].   Table 1). The insets show the saturated load inverter circuit and the inverter response to a square wave input signal with V DD = À40 V. of 2.16 kHz, corresponding to a stage-delay of 46 ls. Examples of the approximately sinusoidal output waveforms of the 5-stage RO obtained at V DD = À16 V and À90 V are shown as insets in Fig. 7. The frequencies attained in our devices are significantly higher than previously reported values (a few Hz up to 300 Hz) for ring oscillators fabricated entirely using mass printing technologies [11,12,14,18] and highly competitive with ROs fabricated from an inkjet-printed small molecule blend onto OTFT structures with 5 lm channel length defined photolithographically [7]. This is particularly encouraging since all our processes, apart from the polystyrene buffer layer, are compatible with a vacuum-evaporation-based R2R process. Subsequent to obtaining the results shown in Fig. 7 and reflecting the improvement in transistor characteristics seen in Fig. 1, the performance of the 7-stage RO also improved with time. When measured with V DD = À60 V, the RO frequency had increased after 1 h to 980 Hz and 3 h later to 1.33 kHz.
Commencing 40 h after fabrication, the 7-stage RO was run continuously with V DD = À60 V for 8 h -equivalent to each inverter undergoing $3 Â 10 7 switching cycles over the period. The performance during that time is given in Fig. 8 where the output frequency is seen to remain essentially constant, rising slowly to a maximum of 1.42 kHz before falling slightly to 1.37 kHz after 8 h of operation. The biggest change in device performance occurred in the peak-to-peak output voltage swing, DV OUT . One day after fabrication DV OUT = 17.3 V, increasing to 22.4 V on day 2. However, during the first hour of continuous operation, DV OUT fell to $12 V, thereafter decreasing only slowly to $10 V (Fig. 8).
Following the period of continuous operation the device was turned off but subsequently tested intermittently during a period of 31 days after fabrication. The results are shown in the inset to Fig. 8. Here we see a continuous degradation in performance with the output frequency tending to stabilize at $500 Hz but with DV OUT decreasing steadily from a high of 28 V to $6 V.
Clearly, since 1 month in storage did not adversely affect the 5-stage RO, the degradation in the performance of the 7-stage device we presume is linked to the 8-h period of continuous operation on day 2. Further work is needed to confirm whether this arises simply from charge trapping or from subtle, electrically-induced chemical changes at the insulator-semiconductor interface such as those described by Di Pietro and Sirringhaus [38] for ntype organic semiconductors.
Simulations of the 5-stage ring oscillator were also carried out using Silvaco's Gateway modeller and the model card for Device 1 (Table 1). Interestingly, these showed that for V DD set to À40 V and À60 V our ROs should be capable of providing operating frequencies of 7 kHz and 20 kHz respectively i.e. more than an order of magnitude higher than observed in practice (Fig. 7).
To investigate the reason for this discrepancy, soon after completing the test measurements in Fig. 7, an inverter from the 5-stage RO was isolated and its response to a À60 V, 1 kHz input square-wave examined (Fig. 9). The 'spikes' seen at the leading and trailing edges of the inverter output arise from capacitive breakthrough from the input signal and are not of interest. The more important features arise from effects related to the load transistor.
(a) The 'pull-up' ability of this transistor is weak. The inverter output reached only À27 V, less than half the rail voltage (V DD = À60 V). Since the load TFT operates in saturation, from Eq. (2) I D (load) is given by where V TL is the threshold voltage of the load TFT, V DD is the rail voltage and V the output voltage of the inverter. In the ideal case of the driver transistor being fully turned off when V G (driver) = 0 V, then the  inverter output of À27 V would correspond to the condition (V DD À V À V TL ) = 0, suggesting a shift in V TL to À33 V as a result of bias stress while acquiring the results in Fig. 7. This is likely to be an over-estimate, however, owing to the non-zero off-current of the driver TFT. (b) When measuring the inverter response in Fig. 9, the buffer amplifier and coaxial cable presented a load capacitance of $48 pF at the inverter output. Owing to the lower on-conductance of the load transistor, the time to charge this capacitance via the load TFT, $0.3 ms, is longer than for discharging through the driver TFT, $0.1 ms. In the case of the RO, the relevant capacitance is the channel capacitance, WLC i $ 10 pF, of the driver TFT of the following stage, suggesting that the RO should be capable of operating well above 10 kHz. However, such considerations neglect the effect of parasitic capacitances, especially gate-source, C gs , and gate-drain, C gd , overlap capacitances.
In Fig. 10 we show the results of simulations in which the effect of these capacitances on the 5-stage RO frequency was investigated. In the simulations it was assumed that V DD = À60 V and that, based on the transistor designs, the gate overlap in the driver transistors was symmetrical so that C gsD = C gdD and that for the load TFT C gsL = 0.2C gdD .
It is obvious that overlap capacitances seriously impair RO operation, with the simulated output frequency decreasing from 20 kHz with no parasitic capacitance to less than 1 kHz when C gdD > 22 pF. When measured directly, C gdD = 35 pF and C gsD = 50 pF owing to slight registration errors during fabrication. According to Fig. 4(c), the aspect ratio of the load transistors in the ring oscillator, W/ L = (400 lm)/(50 lm), is such that parasitic currents would make an even greater contribution to the overestimate of saturation mobility than was observed for the devices in which W/L = (1000 lm)/(50 lm). The true conductance of the load TFTs would have been much greater, therefore, than expected from the designed width, W. In a first approximation to account for this effect, the conductance of the load transistors was doubled by increasing the effective W to 800 lm. With these more realistic values included in the model, the simulated RO oscillated at 1 kHz and close to the measured frequency of 1.12 kHz. Interestingly, had the misalignment error led to a reversal in the values of C gdD and C gsD , the simulated RO frequency would have decreased below 500 Hz i.e. gate-drain overlap capacitance of the driver TFT, C gdD , has a greater degrading effect than the gate-source capacitance, C gsD . Not unexpectedly, therefore, registration and gate overlap capacitances will be important issues to manage in a highspeed R2R process.

Conclusions
We have demonstrated that bottom-gate DNTT transistors with mobility $1 cm 2 /V s can be fabricated routinely and reproducibly with yields P90%. Apart from the polystyrene buffer layer applied to the TPGDA all fabrication steps were based on vacuum-evaporation and compatible with a R2R process. Interestingly, optimum device performance was achieved some 40 h after removing the devices from the evaporator following the final metallisation step. By characterising 90-transistor arrays on each substrate we have obtained statistical information on the likely spread in mobility values as well as on the effect of parasitic source-drain currents which, in smaller devices W 6 1 mm results in the mobility in saturation being overestimated by more than 50%. By choosing TFTs in which parasitic currents were considered negligible, a model card of relevant parameters was derived by simultaneously fitting transfer and output characteristics using Silvaco's UOTFT model. The model card was then applied successfully to simulate inverter operation using Silvaco's Gateway simulator.
Unipolar inverters based on a saturated-transistor load and coupled to a buffer amplifier presenting a load capacitance of 48 pF and with V DD = À60 V, were shown to be capable of undergoing a full switching cycle in $0.4 ms Fig. 9. Response of an inverter stage from the 5-stage ring oscillator (V DD = À60 V). Fig. 10. Effect of parasitic capacitances on the 5-stage ring oscillator frequency deduced from simulations with V DD = À60 V. The inset shows the ring oscillator circuit including parasitic gate-source, C gs , and gatedrain, C gd , capacitances added to the driver (D) and load (L) OTFTs. In the simulation it was assumed that C gdD = C gsD = 5C gsL .
corresponding to a switching frequency of 2.5 kHz. When coupled in series with other inverters to form 5-and 7stage ring oscillators, significantly shorter switching times corresponding to operational frequencies >10 kHz were anticipated owing to the lower load capacitance, $10 pF, presented by the accumulation channel of the driver transistor of the following stage. In the event, the output frequencies of a 5-stage RO ranged from 270 Hz at V DD = À16 V to 2.16 kHz when V DD = À90 V. Simulations showed that the degradation in performance was caused by gate-source and gate-drain overlap capacitances, with the latter having the greater effect because of the smaller size of the load transistor. When these are taken into account, together with an allowance for the parasitic-current-enhanced performance of the load TFTs, a reasonable match between experimental and simulated frequencies was obtained.
We have also shown that a ring oscillator based on DNTT/PS-buffered TPGDA TFTs can operate continuously for 8 h at V DD = À60 V with relatively little change in output frequency albeit that a reduction in amplitude occurs. When tested intermittently over the following month, the RO continued to operate but displayed reductions in both the frequency and amplitude of the output signal. A nonencapsulated RO stored without bias under atmospheric conditions for a month performs as well as a pristine device. We conclude from these observations that continuous operation for long periods initially, can lead to enhanced atmospheric degradation during later storage.
In conclusion, we have demonstrated that functional, environmentally stable organic electronic circuits can be fabricated reproducibly with high yield using low-cost, vacuum-evaporation-based processes that are common in the packaging industry. However, improving circuit performance by minimising gate overlap capacitances must be a key target for future R2R processes.