Flexible thin-film transistors using multistep UV nanoimprint lithography
Graphical abstract
Highlights
► ► A multistep UV nanoimprint lithography process has been demonstrated for the fabrication of flexible thin-film transistors. ► TFTs with channel lengths from 5 μm down to 250 nm have been fabricated on Si and PEN foil. ► On-demand imprint planarization was introduced on flexible foils. ► Charge carrier mobilities of 0.06–0.92 cm2 V−1 s−1 were obtained on Si. ► Charge carrier mobilities of 0.16–0.56 cm2 V−1 s−1 were obtained on PEN foil.
Introduction
In a world following the ever demanding decrease of feature sizes for the fabrication of faster electronic circuits and devices according to Moore’s law [1], research and development of tools allowing reproducible patterning at an ever decreasing scale gain increasing attention. On the other hand, electronics manufacturers focus on reducing fabrication costs and addition of device functionalities. Of great interest in this direction are organic plastic electronics, allowing potentially low-cost fabrication, in combination with the introduction of light-weight, flexibility and transparency, in high throughput roll-to-roll (R2R) or roll-to-plate [2] manufacturing lines. Transparent, bendable and even rollable flexible electronic devices such as organic light-emitting diode (OLED)-based displays [3], radio-frequency identification (RFID) tags [4], [5], and organic solar cells (OSCs) [6] are being pursued. However, flexible electronic devices face new challenges, not necessarily originating from the small dimensions of the device, but from deformations and the dimensional instability of the substrate [7].
In combination with R2R manufacturing for low-cost fabrication of plastic electronics, the high-resolution [8], [9] patterning technique nanoimprint lithography (NIL) is an excellent candidate. The classical thermal NIL [10], [11], [12] has been further developed into UV-based NIL [13], and as repetitive technique into step-and stamp [14] and step-and-flash imprint lithography (SFIL) [15], allowing better control over the residual layer thickness and throughput, by crosslinking a low-viscosity resist by UV irradiation through a fused silica template. Flexible organic thin-film transistors (OTFTs) have been fabricated by photolithographic patterning [7], [16], [17], [18], stamping methods [19] and inkjet printing [20], [21], [22], [23], all showing different advantages and disadvantages regarding layer registration, process temperature, feature sizes and device performance [20], [24], [25]. With conventional printing techniques, typical channel lengths on the order of 10 μm are obtained, limiting the bandwidth to 10 kHz for printable semiconductors with typical mobilities of 0.01 cm2 V−1 s−1 [26]. Fast, sub-micron transistors are, other than with conventional patterning techniques such as photolithography, readily available by NIL, being an intrinsically sub-micron and truly nanometer patterning technique.
In literature, TFTs have been reported with source–drain features patterned by UV NIL on flexible foil in a common gate architecture [27] and on glass with a photolithographically defined gate [28]. TFTs with the source–drain features patterned by thermal NIL and a photolithographically defined gate have also been reported [29]. Common gate TFTs cannot be addressed individually and suffer from parasitic effects (capacitances, resistances, inductances). Multilayered, patterned gate TFTs on the other hand, can be addressed individually in an array and show an improved performance. Fabricating a multilayer electronic device requires a good layer registration and overlay accuracy. Patterning on flexible and wavy foils, showing in-plane instabilities and a high sensitivity to thermal as well as pressure changes, remains a big challenge. With the low-cost and sub-micron patterning technique UV NIL, precise nano- to sub-micron alignment are just as important as critical control over the residual layer thickness (RLT) for the performance of a layer-by-layer fabricated, complex electronic device such as a bottom-contact, bottom-gate TFT. To our knowledge, a fully UV NIL-patterned TFT on foil has not been reported to date.
Here we report a method for fabricating bottom-contact, bottom-gate TFTs on Si and on flexible PEN foil with all functional layers patterned with the fast and low-cost patterning strategy SFIL. The complexity of the device layout is strongly increased with respect to the earlier reported flexible, common-gate TFTs [27] in which only the source–drain layer was patterned by SFIL. In this multilayered device the gate, source–drain and gate via are patterned by SFIL, showing a good layer definition and registration accuracy, even on the dimensionally instable, flexible PEN foils. The flexible TFTs were fabricated with the foil reversibly glued to a carrier (foil-on-carrier; FOC), enhancing the dimensional stability and flatness of the foil to result in a thinner and more homogeneously distributed RLT. An even further improved control over the residual layer was required to transfer all imprinted features of each device layer (gate, contact hole, source–drain) into the underlying functional material (metal, dielectric, metal). The here targeted solution of field-by-field planarization creates for every imprint an individual and flat plateau, ensuring complete removal of the residual layer. The transfer and output characteristics of the here fabricated TFTs on foil will be compared with TFTs fabricated on Si with the identical, fully SFIL-based process.
Section snippets
Design and process scheme
Scheme 1 shows a schematic three-dimensional view of the here fabricated TFTs on Si and foil in a bottom-contact, bottom-gate architecture. The gate, source–drain and contact hole features are patterned by SFIL, while the semiconductor is deposited by inkjet printing. In case of patterning on foil, also the planarization layer is patterned by SFIL. The 200 × 200 μm2 contact pads of the source and drain are connected to three or two 5-μm wide interdigitated fingers separated by a space of 5 μm down
Conclusions
In this paper, the feasibility of UV NIL as a patterning technique for the fabrication of multilayered, electronic devices on Si and PEN foil has been shown. Bottom-contact, bottom-gate TFTs have been fabricated as demonstrators by patterning the entire MIM stack of the TFT by UV NIL, forming the gate, source–drain and contact hole with an alignment precision of 25–200 nm on Si and 50–300 nm on foil. We could only successfully and reproducibly pattern all three layers of the TFT on foil by
Materials and methods
Imprint resist MonoMat and anti-sticking layer RELMATTM were purchased from Molecular Imprints, Inc. An experimental poly(ethylenenaphthalate) foil (PEN, 25 μm thick) was provided by Holst Centre. 6,13-bis(triisopropyl-silylethynyl) pentacene (TIPS pentacene) was synthesized according to literature [44]. Polystyrene (PS) (Mw ≈ 9.58 kDa, PDI = 1.03) was purchased from Fluka. 1,2,3,4-Tetrahydro-naphthalene (tetraline) was purchased from Merck.
Foil-on-carriers (FOCs)
FOCs have been made by reversibly laminating the PEN foil
Acknowledgements
Bas van der Putten is acknowledged for SAM depositions and Karin Tempelaars for foil-on-carrier preparation. The program “Patterning on FLEX systems” of the Holst Centre/TNO is acknowledged for financial and scientific support. Supporting Information is available online from Wiley InterScience or from the author.
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