Three-dimensional Finite Elements Method simulation of Total Ionizing Dose in 22 nm bulk nFinFETs Nuclear Instruments and Methods in Physics Research B

Finite Elements Method simulation of Total Ionizing Dose effects on 22 nm bulk Fin Field Effect Transistor (FinFET) devices using the commercial software Synopsys Sentaurus TCAD is presented. The simulation parameters are extracted by calibrating the charge trapping model to experimental results on 400 nm SiO 2 capacitors irradiated under zero bias. The FinFET device characteristics are calibrated to the Intel 22 nm bulk technology. Irradiation simulations of the transistor performed with all terminals unbiased reveal increased hardness up to a total dose of 1 MRad(SiO 2 ). (cid:1) 2016 Elsevier B.V. All rights reserved.


Introduction
Exposure of deep sub-micron n-channel devices to ionizing radiation degrades electrical performance by inducing leakage paths due to positive charges gathering in the field oxides and at Si/SiO 2 interfaces. This creates off-state current through parasitic devices, that in extreme cases can impede the transistor from turning off leading to major faults and catastrophic failure in Integrated Circuits. We examine Total Ionizing Dose (TID) effects in FinFET devices. FinFETs have been adopted in commercial state-of-theart transistor technologies at and beyond the 25 nm gate length as scaling alternatives to partially and fully depleted Silicon-on-Insulator technologies. The structure of a FinFET is shown in Fig. 1. The active area of the transistor is shaped like a fin and wrapped by the gate which results in very good electrostatic control of the channel. The Source/Drain regions extend on the sides of the fin [1][2][3].
In Silicon-On-Insulator FinFETs, the TID effect has been shown to depend on the geometry of the fin [4,5], while in bulk FinFET technologies its appearance is attributed mainly to charges gathering in the Shallow Trench Isolation (STI) at the neck of the fin [6].
Microscopically, carriers generated in the oxide after irradiation are trapped at imperfections of the crystal structure (E 0 -centers), while interface state creation from diffusion of hydrogen species can also affect device performance [7,8]. The Sentaurus simulation tools can solve rate equations for both effects. However, bulk charge trapping has been identified before as being the main contributing factor in bulk FinFETs. [6,9,10]. In this work, the simple case of charge accumulation within the STI in bulk 22 nm nFinFETs under TID is presented.

Parameter extraction
To derive the parameters for our simulations, 400 nm SiO 2 capacitors were fabricated at the University of Southampton and subsequently irradiated using Co 60 at a Dose Rate of 38.6 Rad (SiO 2 )/s and a total dose of 11.6 kRad(SiO 2 ) [11]. The pre-and post-irradiation results are shown in Fig. 2. The analytically extracted mid-gap voltage shift is À1.5 V.
The simulator model was calibrated to the experimental prerad results using a doping concentration N a ¼ 6:4 Â 10 14 cm À3 and an Effective Oxide Thickness t ox ¼ 390 nm. A Schottky metal/ oxide contact with workfunction of 4.2 eV was also used. The Schottky contact prevented voltage shifts when different amount of traps were defined in the oxide by fixing the electrostatic potential difference in the oxide to a value relative to the barrier height between the metal and silicon. A fixed oxide charge of N ot ¼ 6 Â 10 15 cm À3 was introduced to fit the simulated midgap voltage to the experimental results. Thermionic emission was included in the silicon/oxide interface to accurately describe the current through the heterointerface resulting from irradiation [12].
with _ D, the dose rate (rad(SiO 2 Þ=s), f y the carrier yield and g SiO2 is the 'irradiation factor' given by where q = 2.196 is the density (g/cm 3 ) [14] and w = 18 eV is the energy required to create an electron-hole pair [15]. We are also taking into account that 1 Rad = 6.24Á10 13 eV/g. The carrier yield is calculated using, where E 1 and E 2 and m are fitting parameters given in Table 1, and E is the electric field (V/cm). The fractional yield as a function of the electric field is shown in Fig. 3. These carriers get transported out of the oxide through either the nearest electrode, or through the interface with the silicon. The transport of the electrons and holes is performed using the drift-diffusion model. The parameters for carrier transport are also shown in Table 1. Mobility values were taken from [15]. The transport of holes in SiO 2 occurs much slower than transport of electrons. This is translated to a lower mobility value and trapping mechanisms in defect sites.
Microscopic studies on the types of defects capable of trapping positive charges in SiO 2 have revealed a dimer configuration with a shallow activation energy %1 eV from the valence band edge (E 0 d center) at a concentration of 80% and bistable defects with an activation energy of %4.5 eV from the valence band edge (E 0 c center) at a concentration of 20% [16]. These defects are simulated using effective trapping densities distributed uniformly throughout the oxide. The trapping mechanism is dominated by the drift motion of the holes. The simulated trapping rate is as follows: where f p is the occupational probability (within a range of 0 to 1) of the unoccupied trapping site p t (either E c ' or E 0 d center), p þ t is the density of the trapping sites occupied by holes (cm À3 ), r p = 6.8Â10 À14 cm 2 is the capture cross section of a hole in the defect site and r n = 10 À12 cm 2 is the capture cross section of an electron in the positively charged trapping site which causes the trap to become annealed [17], v n th = 2.042Â10 7 cm/s and v p th = 1.5626 Â 10 7 cm/s are the thermal velocities of the electrons and holes respectively and J n,p are the current densities (A/cm 2 ). n 1 and p 1 are the effective densities of gap states (cm À3 ), given by, where E trap is the activation energy of the trap, E C and E V are the conduction and valence band energies (eV), N C = 8.867 Â 10 18 and N V = 1.931 Â 10 20 the conduction and valence band density of states (cm À3 ).
The shallow E 0 d center gets annealed during or immediately following the radiation exposure. As the shallow traps get annealed, charges are trapped in deep hole trapping sites [18,19]. Therefore, donor traps with an effective activation energy E trap = E V + 4 eV were used in the simulations to account for the charge that did not get annealed at the time of the experimental measurement.
After transient simulation to a total dose of 11.6 kRad(SiO 2 ), the device was solved in quasistationary with the traps frozen at their state. The full C-V pre-and post-irradiation results of the capacitor    Fig. 3. Hole yield as a function of electric field. The simulation parameters were fitted to Co 60 from [13].
sample are shown in Fig. 4. An effective trap density of p t = 10 18 cm À3 was found. This value was used for the FinFET simulations.

FinFET simulations
The 3D structure of the FinFET is shown in Fig. 5. Structural parameters are in accordance to the Intel 22 nm bulk nFinFET High Performance technology node [1] with L g = 30 nm, W fin = 8 nm, H fin = 34 nm and an effective oxide thickness of 0.9 nm. The trench depth of the STI is 120 nm.
The device simulation models include velocity saturation at the gate Si/SiO 2 interface and the density gradient quantization model as calibrated in [20]. The final device characteristics compared to the commercial 22 nm bulk FinFET technology in [1] are presented in Table 2. The saturation current is measured at a gate bias, V g = 0.8 V, and drain bias V ds = 0.8 V. The off-state current is measured at V g = 0 V and V ds = 0.05 V.
There is a direct contact between the gate electrode and the SiO 2 dielectric. This prevents unrealistic accumulation of trapped charge at the interface of the SiO 2 with HfO 2 by allowing the generated carriers to get transported out of the oxide. The carriers also escape through the hetero-interface of the oxide with the silicon.
Initially, the device was solved with uniform fixed positive STI charges. Drain current (I d ) vs V g curves with increasing charge density are shown in Fig. 6. The densities indicated are areal charges projected to the Si/STI interface. Off-state current in the transistor starts increasing at 1.3 Â 10 12 cm À2 , while the transistor fails to turn off completely at a density of 2.6 Â 10 12 cm À2 and beyond.
The simulation results with fixed STI charge were compared to radiation simulations where all terminals were unbiased. The density of trapped holes in the STI is shown in Fig. 7 for two total doses of 500 kRad(SiO 2 ) and 1 Mrad(SiO 2 ). Due to the absence of bias, the   trapped charge is symmetric between the Source and Drain sides. Concentration is lower underneath the gate, where the parasitic electron channel from the Source to the Drain is expected to appear. The trapped charge profile reflects the electric field in the oxide created due to the doping profile in silicon. This is also shown in Fig. 8. The negatively charged Boron impurity atoms attract holes with a higher intensity towards the top of the neck of the fin. The charge density has a peak located 25 nm below the STI surface. The areal trapped charge projected at the interface at that location is 1.34 Â 10 9 cm À2 at 500 kRad(SiO 2 ) and 7.55 Â 10 10 cm À2 for 1 MRad(SiO 2 ), which is lower than the areal charge required to invert the parasitic channel as was found during the fixed charge simulations presented in Fig. 6.

Conclusions
Three-dimensional simulations of TID in bulk nFinFET devices using the commercial software Sentaurus device were presented.
Based on previous studies on bulk FinFETs, hole trapping in the STI is the dominant cause of device degradation. Calibration of the charge trapping model to 400 nm SiO 2 capacitors revealed an effective bulk trap density of 10 18 cm À3 . The 22 nm bulk nFinFET device characteristics were calibrated to a commercial transistor technology. Fixed oxide charge simulations were used to locate the areal charge at which inversion of the parasitic transistor occurred. The radiation simulations provided insight into the location and profile of the charge trapped in the STI. Increased hardness of this technology to TID was shown, which indicates its suitability for use in harsh environments of increased ionizing radiation. The simulation model can be extended to include the effects of interface trap formation.  as well as the use of the IRIDIS High Performance Computing Facility, and associated support services at the University of Southampton. Data published in this paper are available from the University of Southampton repository at http://dx.doi.org/10.5258/SOTON/ 400301.