Simulations and Performance Studies of a MAPS in 65 nm CMOS Imaging Technology

Monolithic active pixel sensors (MAPS) produced in a 65 nm CMOS imaging technology are being investigated for applications in particle physics. The MAPS design has a small collection electrode characterized by an input capacitance of ~fF, granting a high signal-to-noise ratio and low power consumption. Additionally, the 65 nm CMOS imaging technology brings a reduction in material budget and improved logic density of the readout circuitry, compared to previously studied technologies. Given these features, this technology was chosen by the TANGERINE project to develop the next generation of silicon pixel sensors. The sensor design targets temporal and spatial resolutions compatible with the requirements for a vertex detector at future lepton colliders. Simulations and test-beam characterization of technology demonstrators have been carried out in close collaboration with the CERN EP R&D program and the ALICE ITS3 upgrade. TCAD device simulations using generic doping profiles and Monte Carlo simulations have been used to build an understanding of the technology and predict the performance parameters of the sensor. Technology demonstrators of a 65 nm CMOS MAPS with a small collection electrode have been characterized in laboratory and test-beam facilities by studying performance parameters such as cluster size, charge collection, and efficiency. This work compares simulation results to test-beam data. The experimental results establish this technology as a promising candidate for a vertex detector at future lepton colliders and give valuable information for improving the simulation approach.


Introduction
Lepton colliders have been established as the highestpriority next collider by the European Strategy Update for Particle Physics [1].Vertex detectors are an essential part of experiments at such colliders.They require simultaneous advances in material budget, granularity, and spatial and temporal resolution.Monolithic CMOS sensors are promising candidates given these requirements and have the advantage of cost-efficient mass production capabilities in commercial foundries.The TP-SCo 65 nm ISC imaging CMOS technology is currently being studied for applications in particle physics.Introducing this node size in high energy detectors will improve the in-pixel logic density and/or will allow for a reduction in the pixel pitch.
Monolithic active pixel sensors (MAPS) can be produced with a small or a large collection electrode.This work explores the small collection electrode type MAPS motivated by the small intrinsic capacitance (in the or-Table 1: Requirements for vertex detectors at lepton colliders.Derived from sources such as [7].

Parameters
Requirements Material Budget <1% X 0 Single-point Resolution ≤ 3 µm Time Resolution ∼ ns Granularity ≤ 25 µm × 25 µm Radiation Tolerance > 10 11 n eq /cm 2 der of fF) and, hence, a large signal-to-noise ratio.The activities are carried out within the context of the TAN-GERINE Project [2,3,4], which aims to develop the next generation of silicon detectors for vertex-finding at future lepton colliders.To achieve this, the performance targets shown in Table 1, must be fulfilled.The developments are pursued in collaboration with the CERN EP R&D program [5] on technologies for future experiments and with the ALICE ITS3 upgrade [6].The collaboration included a common foundry submission for test chips in the TPSCo 65 nm CMOS technology, as well as device characterization and generic simulations validating the sensor design for appropriate performance.From this first submission, two test structures have been tested.The DESY Chip V1 (designed at DESY) features a Krummenacher charge-sensitive amplifier and was characterized in [3].The Analog Pixel Test Structure (APTS) [8,9] (designed at CERN) is a technology demonstrator with analog readout designed to characterize different sensor layouts and is part of the studies for the ALICE ITS3 upgrade.
This work presents the test-beam characterization of an APTS, a description of the simulation approach, and a first comparison between experiment and simulations.

Sensor Layouts
The sensor design consists of a thin high-resistivity pdoped epitaxial layer grown on a low-resistivity p-doped substrate.The n-well and p-well are, respectively, the collection implant and the structure that hosts the inpixel electronics and shields them from the electric field of the active sensor region.This base design is the standard layout [10], characterized by a bulb-shape depleted volume around the collection implant.
Design modifications can improve the electric field configuration inside the sensor.The n-blanket layout [11] introduces a blanket layer of n-doped silicon in the p-type epitaxial layer, creating a deep planar pnjunction and enlarging the depleted volume of the sensor.However, this layout leaves an electric field mini-mum under the p-well at pixel edges and corners, leading to slow charge collection and possible efficiency loss in these regions [12].The n-gap layout [13] corrects for this by introducing a gap in the n-blanket under the pwell.This produces a vertical pn-junction that generates a lateral electric field in the farthest position from the readout electrodes (pixel boundaries), pushing charges produced there toward the pixel center.This work is focused on the performance of the n-gap design, whose layout scheme is shown in Figure 1.The electric field and depleted volume for each design can be found in [4].
These designs were originally developed in a 180 nm CMOS imaging technology, and similar developments have been implemented in a 65 nm CMOS imaging process as well [14].The sensors are biased with a fixed positive voltage on the pixel electrodes and a negative bias voltage on the p-well electrode and the substrate.The voltage is the same on the p-well and substrate in these studies.

Detector and Readout System
The APTS [8] is a demonstrator designed for sensor characterization in the TPSCo 65 nm CMOS technology.Each chip comprises a 6 × 6 matrix of square pixels, of which only the central 16 pixels are read out.The chips are available in all three sensor layouts, different doping variants, pixel geometries, and pixel pitches [9].The device characterized in this work has an n-gap design with a 25 µm pixel pitch; each pixel is DC coupled to the front-end electronics.Both in-pixel and periphery circuits contain two source-follower stages as buffered analog output.
The data acquisition setup comprises a custom chipboard for the APTS and the modular Caribou system [15,16] consisting of open-source hardware, firmware, and software for prototype integration.Its key component is a System-on-Chip board (Xilinx Zynq) that runs the data acquisition software and firmware for powering, configuration, control, and readout of the prototype.A mezzanine board, the CaR board, provides current sources, voltage sources, and a physical interface to the chip.This board is used for efficiency studies and includes two 8-channel ADCs that sample the analog output signals of all pixels at 65 MS/s.
Pulse injection measurements have been used to determine gain non-linearities and pixel-to-pixel variations.An absolute calibration of the gain curves was performed using the K-alpha line of an 55 Fe source.The measured noise is about 30 electrons.More details on the DAQ system and calibration are reported in [4].

Test-Beam Setup
Test-beam studies allow for the characterization of new detector prototypes for particle physics applications under realistic conditions.
The test-beam setup consists of a MIMOSA26 telescope [17], composed of six planes and used for beam particle track reconstruction.The device under test (DUT), in this case, the APTS, is placed between the third and fourth telescope planes.The TelePix [18] detector is used as a trigger plane with a configurable acceptance window and is the last detector plane downstream.Finally, a Trigger Logic Unit (TLU) [19] manages the trigger signals of the setup to synchronize the data acquisition between all the devices.
The employed data acquisition software is EU-DAQ2 [20], which controls the storage and synchronization of data from all systems.The data analysis framework for online monitoring and offline event building is Corryvreckan [21].
Two triggering schemes have been employed.To find the position of the DUT relative to the beam telescope, it was operated in self-triggered mode.To allow for unbiased efficiency measurements, it was triggered externally using TelePix, where a mask was applied to trigger on only a small region around the DUT.
The test-beam campaigns have been carried out at DESY-II [22], with a 4 GeV electron beam and a maximum beam particle rate of 5 kHz.

Test-Beam Characterization
This section describes the reconstruction procedure of the test-beam data and discusses the results of cluster size and efficiency studies.

Data Analysis
When the DAQ receives a trigger, the respective waveforms are recorded.These are processed for each pixel during the data analysis; their amplitude is measured and transformed to charge using the calibration mentioned in Section 3.
To calculate the amplitude, two regions are defined: the baseline region (1 µs interval before the pulse starts) and the peak region (1.5 µs interval around the expected pulse maximum).The baseline is obtained by averaging the values in the baseline region.The maximum of the pulse is taken from the peak region, and the amplitude is obtained by subtracting the baseline from the maximum value.A threshold is applied to define pixel hits.The studied thresholds are in the typical operating range, from 90 (∼ 3σ noise ) to 400 electrons.
Individual hits on the same device that belong to the same particle interaction are grouped into a cluster based on spatial vicinity.The employed clustering method reconstructs the cluster position and charge by defining a seed pixel (pixel with the largest signal) and adding all the adjacent pixels with signal above thresholds.Then, the cluster position is calculated as the charge-weighted center of gravity.
The tracks of the beam particles are reconstructed using the telescope data; a fit is made using the General-Broken-Lines algorithm [23], which considers the scattering of particles when passing through a material.
Finally, the clusters on the DUT are associated with reconstructed tracks within 30 µm diameter window to study hit detection efficiency and cluster properties.

Cluster Size
The mean cluster size is obtained by calculating the mean of the distribution in a cluster size histogram.It is highly dependent on its charge-sharing properties, which are regulated by the charge transport mechanism.In depleted areas, the movement of free charges is dominated by drift, usually directly towards the collection electrode.While in non-depleted areas, they move mainly by diffusion, producing a wider charge distribution and increasing charge sharing between the pixels.
Figure 2 shows the mean cluster size as a function of the threshold, comparing the n-gap layout at different bias voltages.No significant difference is observed because the depleted volume in the sensor remains approximately constant for all bias voltages.
Within the operating thresholds, the n-gap design exhibits a mean cluster size ranging from 1.6 to less than 1.1 pixels.These results agree with the expectations from the design since the large depleted volume and the high lateral electric field in the edges constrain the charge-sharing effects.

Efficiency
The detection efficiency of the detector is calculated as the ratio of the associated clusters in the DUT and the reconstructed tracks within the acceptance window around the cluster center.
Figure 3 compares the efficiency performance as a function of the threshold for the n-gap design at different bias voltages.The results are very similar since the depleted volume and the charge sharing in this layout are almost unchanged with the bias voltage.In the operating threshold range (above 3σ noise ), the efficiency for the n-gap design starts at 99.9% and falls to 86%, and remains above 99% until a threshold of 220 electrons.

Sensor Simulations
The electric field distribution in sensors greatly depends on doping profiles.In particular, MAPS with a small collection electrode have highly complex electric fields.Hence, sensor simulations are necessary to understand the inner workings of the detector.This work uses a combination of TCAD and Monte Carlo simulations to obtain precise electric fields and high statistic results for detector performance evaluations [24].

TCAD Simulations
The TCAD simulations carried out within the TAN-GERINE project are based on fundamental principles of silicon detectors and employ generic doping profiles as described in the following.A 3D structure is created with geometrical operations and analytic doping profiles following the scheme shown in Figure 1.
Quasi-stationary simulations were performed to model the electric fields of the studied designs.These simulations aim to understand the effect of design changes and provide input for optimization of the design and the operational parameters.This was achieved by scanning over different geometrical and operational parameters of the sensor, such as p-well opening and bias voltage, and observing the behavior of the electric field, the lateral electric field strength, as well as the depleted volume.Finally, the parameters that reproduce the expected physical behavior (similar to previous studies on other technologies [10,11,13]) are selected to derive electric fields for subsequent Monte Carlo simulations.More details on this simulation approach can be found in [4].

Monte Carlo Simulations
Monte Carlo simulations are employed to model the full response of a detector.This is achieved with the modular framework Allpix 2 [25], developed for Monte Carlo simulations of semiconductor radiation detectors.The results of these simulations allow for direct comparison with experimental data.
The simulated detector structure consists of a matrix of square pixels with a 25 µm pitch and a sensor thickness of 50 µm (including epitaxial layer and substrate).
The electric field for each pixel cell is imported from the TCAD simulation described above.A 4 GeV electron beam is used as a particle source to compare with the test-beam results.The data processing is analog to the one described in Section 5 for test-beam data.The most significant observables that can be obtained are detection efficiency, cluster size, spatial resolution, and charge collection.Initial results from Monte Carlo simulations using generic TCAD fields have been reported in [2], and the most recent results on efficiency and charge collection are compared with test-beam data in the following section.

Comparing Data and Simulation
Simulations are compared to experimental data in order to validate the employed simulation approach.In figure 4, both charge distributions follow the trend of a Landau distribution convolved with a Gaussian, representing effects in the interaction of minimum ionizing particles traversing thin sensors, such as stochastic fluctuations of charge deposition and electronic noise.This convolved function is fitted to extract the most probable value (MPV) for the charge collection.The obtained MPVs are around 500 electrons.Figure 5 shows that the agreement between experimental data and simulations for the detector efficiency is within 1%, only considering statistical uncertainties.Ongoing studies of a detector in the standard design show a slight disagreement between simulations and experimental data.The different compatibility depending on the sensor layouts can be explained by the susceptibility of the standard layout to effects due to charge mobility dominated by diffusion.This makes the standard design more sensitive to parameters such as carrier lifetimes.Further studies are planned to understand the origin of these differences.

Summary and Conclusions
Given their low material budget and improved performance parameters, MAPS produced in the TPSCo 65 nm CMOS imaging technology are a promising proposal for vertex detectors at future lepton colliders.
Different small collection electrode MAPS technology demonstrators have been studied through test-beam characterization and simulations.The efficiency, mean cluster size, and charge distribution have been investigated for the n-gap design.Results show a consistent behavior with the same design studied in a 180 nm technology; there are no significant differences in the efficiency and mean cluster size for the investigated bias voltages.The overall mean cluster size is small because of the charge-sharing effects constrained by the enlarged depleted volume and the high lateral electric field at the edges.
Simulations have been performed with a combination of TCAD and Monte Carlo frameworks on a sensor structure using generic doping profiles.The device simulations on TCAD produce the complex electric fields characteristic of small collection electrode MAPS.Monte Carlo simulations produce performance parameters that are directly comparable to experimental data.Simulations for the n-gap design exhibit compatibility with experimental data, opening a promising path toward validating them.
The next prototypes under study have been produced in the second submission to the foundry: DESY Chip V2, which includes full in-pixel functionalities, and H2M (hybrid-to-monolithic), including in-pixel analog and digital processing electronics and a pixel matrix of 64 × 16.These prototypes are being investigated using the same methods presented here.

Figure 1 :
Figure 1: Scheme of the n-gap sensor design.Structures not to scale.

Figure 2 :
Figure 2: Mean cluster size as a function of the threshold for APTS in n-gap layout at different bias voltages, from -1.2 to -4.8 V.Only statistical uncertainties are included.

Figure 3 :
Figure 3: Efficiency as a function of the threshold for APTS in n-gap layout at different bias voltages, from -1.2 to -4.8 V.Only statistical uncertainties are included.
Figures 4 and 5 show, respectively, the comparison of the seed pixel charge distribution and the efficiency as a function of the threshold for a detector in the n-gap design.Both plots show a good agreement between simulation and experimental data.

Figure 4 :
Figure 4: Comparison of experimental data and simulations of charge distribution of the seed pixel for the n-gap layout at -4.8 V bias voltage.

Figure 5 :
Figure 5: Comparison of experimental data and simulations of efficiency as a function of the threshold for the n-gap layout at -4.8 V bias voltage.Only statistical uncertainties are included.