Intelligent Front-end Electronics for Silicon photodetectors (IFES)

While high channel density can be easily achieved for big experiments using custom made microchips, providing something similar for small and medium size experiments imposes a challenge. Within this work we describe a novel and cost effective solution to operate silicon photodetectors such as silicon photo multipliers (SiPM). The IFES modules provide the bias voltage for the detectors, a leading edge discriminator featuring time over threshold and a differential amplifier, all on one printed circuit board. We demonstrate under realistic conditions that the module is usable for high resolution timing measurements exploiting both charge and time information. Furthermore we show that the modules can be easily used in larger detector arrays. All in all this confirms that the IFES modules are a viable option for a broad range of experiments if cost-effectiveness and small form factor are required. & 2016 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY license (http://creativecommons.org/licenses/by/4.0/).


Introduction
One of the main challenges that small and medium sized experiments face is reading many detector channels with high channel density and for a reasonable price. The big experiments can solve this issue by construction of application specific integrated circuits (ASIC) like the NINO [1] chip, the SPIROC [2], or the MAROC [3]. Developing or operating an ASIC is not realistic for experiments with low channel density, therefore standard equipment is used. A typical setup for operating silicon photo multipliers (SiPMs) for a small or medium sized experiment consists of a bias supply, a discriminator and an amplifier for every readout channel in the setup.
To address this problem a small versatile and compact frontend module was developed. The Intelligent Front-end Electronics for Silicon photodetctors (IFES) module is made of standard, industry grade and off the shelf available components. The IFES module features a current stabilized bias voltage source, a broad band differential amplifier and a leading edge discriminator with time over threshold (ToT) signal for very affordable production costs of less than 50 Euros per channel. Current boards feature two channels with an overall dimension of 80 Â 32 mm 2 . The system can be remotely controlled for both bias voltages and discriminator thresholds. For basic operation without remote control the only connection required is the one to the detector and to an ADC or TDC readout module afterwards. The IFES module provides an easy to use, cost-effective, high channel density and low noise detector readout.

Electronics
In Fig. 1 the block diagram of the IFES modules is shown. Section A displays the relation of the bias voltage supply, differential amplifier and leading edge discriminator. Section B shows the main power supply of the board and Section C shows the internal bus system.
The bias voltage is produced by a Boost DC/DC converter (Linear Technology LT3482 1 ). The output of the converter produces a feedback loop with the aid of a current mirror. Together with a current amplifier this ensures that the bias voltage is stabilized while being controllable via a digital to analogue converter (DAC). A bias voltage calibration is foreseen, by measuring the dark current on the measuring port (compare Fig. 2), and tuning the bias voltage till a defined dark-current is reached. The pulse produced by the SiPM is read out as differential balanced signal over a twisted pair cable. The differential signal is received by a broad band amplifier (Analog Devices AD8351). We measured that the differential setup allows for a cable length up to 50 cm between SiPM and IFES module without signal distortion. In case no precise timing is required the cable length can be up to 10 m for counting experiments. The input stage has similar features as the NINO [1,4] chip. After the amplification stage the signal is provided to the user as analogue differential signal. This signal is fed to the leading edge discriminator. Noise reduction was one of the main design goals for the IFES module. To ensure proper operation in harsh environments like accelerator facilities all signals are differential. This also suppresses the formation of ground loops between detector and IFES module and between the IFES module and the readout electronics. Following the LVDS standard, the connection can withstand a potential difference of 71 V between transmitter and receiver ground. It follows that good grounding is essential for successful operation of the experiment. If required, the IFES modules can be grounded by closing a soldering bridge on the board.
By changing a single resistor on the boards the IFES modules can be adapted to support various detector types with a bias voltage up to 90 V. Most SiPMs currently available on the market operate with a bias voltage between 20 V and 70 V. Depending on the model two to three SiPMs can be operated in serial connection. Under normal conditions the amplification of the boards is fixed. If required it is also possible to change fixed amplification by replacing one resistor on the board. In Fig. 2 a fully assembled IFES module with two channels is displayed on the left side. The right graph shows a typical signal produced by an IFES module in combination with an Advansid ASD-RGB3S-P (3 Â 3 mm 2 active surface) and a plastic scintillator (EJ-200). The measurement was done with a CEAN V1742 waveform digitizer. To simultaneously record the digital ToT pulse the LVDS signal was converted to a NIM signal. The rise time (10-90%) of the analogue signal is 6.1 ns.

Operation principle
The modules are constructed in a way to allow the readout of large detector arrays. This is done by daisy-chaining several modules. The supply voltage for the modules can be connected from one module to the next allowing the supply of several modules by one low voltage power supply (7-20 V). The slow control of the boards can be done with any micro controller or single board computer featuring the serial peripheral interface (SPI) bus. Connecting the control bus in a daisy chain was made possible by the choice of a DAC (Maxim Integrated MAX5135) that issues a ready signal after an instruction is processed. This ready signal is used to select the DAC chip on the next IFES module in the daisy chain. The LVDS drivers ensure proper quality of the signals even for long signal paths. This was tested for cable lengths up to 10 m under laboratory conditions and in an accelerator environment.
By issuing sequential commands to the on-board DACs the controller can set all bias voltages and thresholds individually. Theoretically, the design does not limit the number of channels per controller. In case of the ASACUSA [5] antihydrogen detector [6] at the CERN antiproton decelerator (AD) facility 128 channels  resulting in 64 modules were successfully operated by a single Arduino micro controller board.

Experimental setup
Measurements for timing resolution have been performed in January 2014 as a parasitic experiment at the JESSICA beamline at the COSY facility of the Forschungszentrum Jülich in Germany with a 1.471 GeV/c proton beam. The tests were done using EJ-232 (SC1) and EJ-228 (SC2) scintillators with dimensions 28.5 Â 28.5 Â 5 mm 3 as detector material. KETEK 3350TS and KETEK 3360TS SiPMs (3 Â 3 mm 2 surface area and 50 Â 50 μm 2 and 60 Â 60 μm 2 micropixel size and optical trench separation) were used as photodetectors [7,8]. The SiPMs were mounted on opposite sides on the center of the small surfaces of the scintillator. All signals were recorded using CAEN V1742 VME waveform digitizers operated at 5 GHz sampling rate. The analysis of the waveforms was performed using a self-library [9], ROOT [10] and rootpy [11]. The bandwidth was limited by a software Fourier filter to 204 MHz.
Further tests for the correlation between digital ToT signal and analogue pulse height have been performed in the laboratory with an oscilloscope.

Performance
For evaluation of the timing performance the time of flight (ToF) spectra between the reference counter and the detectors SC1 and SC2 and in between those detectors were measured. The reference signal was produced by calculating the mean time of three scintillators that were read by two photomultipliers each.
The ToF measurements used for the determination of the timing resolution for the detectors is shown within the left graph of Fig. 3. During the parasitic test beam experiment the main goal was to test every part of the IFES modules under realistic conditions. The board was evaluated with respect to stability of the analogue and digital signals and reproducibility of bias voltage and discriminator threshold settings. It follows that the achieved timing resolution should be considered as easily achievable with the described detectors without tuning the system for high resolution timing.
The correlation between analogue pulse height and ToT signal features two linear regions. After measuring this relation it is possible to use the ToT signal in combination with a multi-hit TDC to measure charge deposit and timing in the same instance. A measurement of this relation is displayed in Fig. 3 on the right side. Furthermore timewalk correction of the leading edge timestamp is possible with the ToT signal.

Summary
A novel front-end module for silicon photodetectors was developed. The IFES module can be tuned to provide bias voltages up to 90 V. It featured differential silicon photodetector readout and a fully differential signal path hence reducing pickup noise even in hostile environments like accelerator facilities. The modules combine the bias voltage, an amplifier and a discriminator on a single board with dimensions 80 Â 32 mm.
The modules were successfully tested under laboratory conditions and in a beam facility. They are in active use at the antihydrogen experiment of the ASACUSA collaboration at the CERN AD where 64 boards are operated by a single micro-controller in a daisy-chain.
Furthermore a per channel price of less than 50 Euro was reached while providing accurate timing capabilities, differential analogue signals, a leading edge time over threshold discriminator and remote control for individual channels.