Novel method of alignment to buried cavities in cavity-SOI wafers for advanced MEMS devices

Accurate alignment between the cavities in cavity-SOI (c-SOI) wafers and lithography on the wafer surface is essential to advanced MEMS production. Existing alignment methods are well defined, but often require specialized equipment or costly software packages available only in professional manufacturing environments. It would be beneficial for the microfabrication world to be able to utilize standard alignment techniques and tools that are easily available also in smaller MEMS fabrication units and especially the majority of research facilities. Therefore, we demonstrate a feasible method for c-SOI wafer alignment using an ASML PAS5500/100 wafer stepper with standard software configuration by relocating ASML alignment markers towards wafer's edges and utilizing a terracing process to reveal them for alignment. Moreover, we characterize the magnitude and behavior of image offset errors that are introduced using this method. The offset error is found to be inversely proportional to the value of the coordinate in each axis, resulting in images being shifted towards the center of the wafer. The measured offset errors are< 160 nm, and are suitable for most applications. To further minimize these errors we propose a simple model or database of the offsets. We conclude that this alternative alignment method is feasible for a number of MEMS applications, and could promote increased integration of c-SOI technology into advanced MEMS production.


Introduction
Cavity-SOI (c-SOI) wafers are an emerging form of advanced substrates used in MEMS processing, which feature cavities below the buried oxide (BOX) layer. In most cases, cavities are etched into a silicon handle wafer, on top of which a silicon wafer is bonded and thinned to produce a device layer, such that MEMS can be fabricated over the cavities [1][2][3][4]. These cavities are used to simplify manufacturing [5] or can be integrated into the active, passive or structural elements of the MEMS device [6,7], see Fig. 1. Integration of CMOS and MEMS with cavities has been successful, as demonstrated by commercial availability of pressure sensors and accelerometers in smartphone and automotive applications [7][8][9]. The realization involves alignment of CMOS wafer to MEMS wafer with either having a cavity, while the alignment and bonding is achieved with industrial wafer alignment tools as the final step [8,10,11]. The utilization of c-SOI substrates can further increase the complexity of 3D devices that can be made, while maintaining compatibility with CMOS processing. Therefore, c-SOI substrates are increasingly used in various microfabrication applications [1][2][3][4]7,12]. For correct integration, lithography on the device layer must precisely correspond to the cavities hidden beneath it. Currently the alignment of the device layer to the cavities is still challenging. Overcoming this challenge would push forward the development of devices, that require advanced silicon structures such as next-generation CMOS-MEMS/NEMS [7,13,14], novel and highly integrated biomedical MEMS for implantables [15][16][17][18][19], smart drug delivery [20], catheter-based instruments [21,22], minimally invasive surgery [23,24] and fundamental cell/tissue biology [25][26][27]. Therefore, an effective and accurate method of aligning these two layers is essential.
Different methods to achieve such alignment are available. buried structures and align them to a pre-fabricated device layer that is bonded on top [10,28] with sub-μm accuracy [29]. However, this method requires specialized equipment, which is not widely accessible, and specialized alignment markers [10,28,29]. An alternative approach is to place alignment markers on the back-side of the wafer, to which the cavities and top devices are both aligned [10,30]. This method however does not yield sub-μm accuracy [10,30] and is infeasible for wafer bonding due to front-side contamination when patterning markers on the back-side. Therefore, it is necessary to define a process whereby alignment to a pre-fabricated c-SOI wafer can be achieved using non-specific front-side alignment markers.
To this end, a new method is presented using processes commonly used in microfabrication facilities, e.g. a wafer stepper (ASML PAS5500/100) and dry etching, without expensive software-or hardware modifications. This wafer stepper detects markers on the substrate, which are simple diffraction gratings, by illuminating them with a 633 nm laser and tracking the diffracted beam with a photodiode system. An alignment feedback loop positions the wafer such that the markers provide optimal diffracted signal [31]. This alignment method is suitable for thin film 2D microfabrication, but needs to be extended to allow for true 3D microfabrication. To do so, we propose a method that involves patterning ASML alignment markers on the front-side of the handle wafer beneath the BOX layer. These alignment markers are to be detected through/below the top device layer and subsequently used to pattern new alignment markers on top of the device layer. The new markers would serve for further lithography of the device layer. The challenge is to detect the alignment markers with the alignment system, and to achieve sub-μm alignment of the top surface, on the device layer, to the pattern below the BOX on the handle layer. The alignment is analyzed through the measurement of offsets of the patterned alignment markers.

Detection of alignment markers
The PAS5500 wafer stepper detects markers on the substrate, using a 633 nm laser alignment system. The marker position is subsequently measured using laser interferometry with an accuracy of~0.08 μm, allowing computation of the wafer's position relative to the stepper's projection optics [31]. Previous work has shown that certain alignment markers buried beneath the silicon device layer can be viewed with visible wavelengths provided the layer is suitably thin, e.g. 80 nm [32]. However, much thicker device layers, up to 80 μm for some novel MEMS applications [16], may inhibit optical detection of the markers. Modeling the attenuation of the diffraction signal suggests strong signal drop, falling below the detection limit of the wafer stepper. Proof-ofconcept experiments for this scenario would be informative, but are impractical in this work, as they require manufacturing tools for producing the actual SOI wafer with alignment markers in the handle layer.
For these reasons, an alternative method is devised, involving relocation of the markers to the wafer edge, in order to take advantage of a 'terracing' process, common for SOI wafers. This process removes silicon from the edge of the device layer during SOI manufacturing by beveling. Non-standard positioning of the alignment markers to within 4 mm of the wafer edge places them in the terraced region (see Fig. 2A), thus revealing the markers for optical detection after beveling.
Several problems are anticipated with this process, such as edge effects during lithography, where exposure is performed on or near the edge bead, possibly resulting in dosage variations leading to imperfect marker exposure. Furthermore, the wafer edge can be exposed to debris and contamination during handling that cause micromasking effects during etching. Moreover, variability in dry etching at the wafer's edge could cause problems, because the diffraction intensity is optimal for a certain alignment marker depth. Furthermore, subsequent lithography  of c-SOI could leave resist on the alignment markers, effecting their reflectivity. Therefore, the key parameters to control and measure are the locations of the markers, specifically, their proximity to the wafer edge, and their subsequent detectability in the wafer stepper.
Five silicon wafers (6 in. diameter, 675 μm thick, < 100 > orientation) were spin coated with 1300 nm of HPR504 positive photoresist, which was exposed with the alignment marker pattern in the wafer stepper. Each wafer featured eight pairs of markers placed at intervals in the range of 0.8 mm-4 mm from the wafer edge (see Fig. 2B); 0.8 mm being the minimum optical clearance required on all sides of a marker, and 4 mm being the limit of the available terracing process. Following resist development, for two wafers the markers were dry etched in silicon (SPTS Pegasus DRIE etching tool) with a target depth of 140 nm (~0.25*wavelength of diffraction laser), after which the resist of these two wafers was stripped in oxygen plasma. The etched depth was measured with stylus profilometry (Dektak XT, 2.5 μm tip) on one wafer to quantify edge effects. The wafers were then re-inserted into the wafer stepper, with a special program to locate, focus and align to each respective pair of markers. The three wafers with markers-in-resist served to mimic lithography conditions in subsequent device layer patterning, when spin coated resist can reduce reflectivity of alignment markers. The two wafers with markers-in-silicon served as a control of maximum reflectivity.
No edge effects were visible after spin coating. Following exposure and etching, it was found that markers nearest to the wafer's edge were over-etched by up to 14 nm over the target depth of 140 nm (see online Supplementary Fig. S1), possibly due to higher concentrations of etchant species in this region. Marker depths approached the target depth as distance from the wafer edge increased. Subsequent re-insertion into the stepper resulted in successful location and alignment of all specimens. Furthermore, analysis of the signal quality from each marker, a relative metric computed by the stepper, showed no significant variation with respect to distance from the wafer's edge (see online Supplementary Fig. S2). The signal quality SQ was constant with the position of alignment markers. It was high (SQ =~85%) for silicon surfaces and adequate (SQ =~35%) for silicon wafers on which the markers were patterned in resist. Offset in focus for the resist-coated wafers served as worst alignment condition and showed no significant change of SQ either. This indicates that the alignment system is robust to edge effects on the markers and the surface reflectivity. Furthermore, the marker over-etch had no negative effect on the quality of the signal returned and alignment was successful with all tested markers. However, to avoid edge effects, the optimal position of alignment markers should be as far from the edge as possible while maintaining a distance of 0.8 mm from the terrace edge. This is to avoid obstruction of the light beam by the terrace.

Multi-height alignment on thick device layers
The second technical challenge arises from the fact that the alignment markers lie at a different height to the wafer's top surface. Alignment markers are placed at the surface of the handle layer of the c-SOI, while processing occurs on the surface of the device layer. When aligning wafers, the wafer stepper initially levels the wafer by detecting its surface and vertically translating the stage to ensure the surface lies within the focal range, specified as ± 25 μm for this wafer stepper [25,26]. For c-SOI wafers with thick device layers, device thickness > 50 μm, the focusing would be out of specification. Therefore, we investigate problems introduced by height difference of up to 80 μm between the top surface plane and the plane of the alignment markers. Anticipated problems include failure to align, out-of-focus exposure of patterns on the top plane and position errors in those patterns. Therefore, the key parameters to measure are the ability of the stepper to align to the markers, as well as the offset of patterns exposed at the surface of the device layer.
The method devised to test this involved creating proof-of-concept wafers that geometrically simulate the c-SOI wafer having a thick device layer. A terrace was created, which mimicked the device layer, while alignment markers in the silicon substrate simulated the alignment markers of the cavity pattern in the handle layer. Coating the terrace with positive photoresist allowed exposure of new features on top to characterize the key parameters. These features were again alignment markers, because the wafer stepper has built-in metrology to measure their position. The offset was then determined as the difference between the target position and actual measured position of each marker.
The fabrication of the proof-of-concept wafers commenced with lithography and etching of alignment markers on silicon monitor wafers at 1.2 mm from the wafer edge (see Fig. 3A). Two approaches were considered to simulate the device layer using thick polymeric layers. On one set of wafers, AZ40XT photoresist was spin coated to an average thickness of 30.0 μm (SD = 0.2 μm), followed by a 5 mm edge bead removal to create a terrace in the resist, and finally a hard bake according to manufacturer specifications. On the other wafers, 80 μm thick self-adhesive polyimide foil was manually applied, then selectively cut and peeled around the wafer edge to create the terrace. These approaches provided effective methods of quickly simulating thick device layers without encountering difficulties involved in wafer bonding. Each simulant device layer was sputter coated with 100 nm of Al(1 wt %)Cu for optical opacity, to ensure that this plane would be detected as the wafer surface during the leveling operation in the stepper. As a control situation, a control wafer was made without the device layer or metal to benchmark the offset error in case of regular lithography. All wafers were then spin-coated with 1300 nm of HPR504 positive resist, with a 5 mm edge bead removal to remove any resist covering the alignment markers in the silicon substrate. The wafers were aligned in the wafer stepper using these markers and 9 new markers in the resist at the top surface plane in a range of locations (see Fig. 3B). These markers were developed in the resist, but not etched. The wafers were re-placed in the stepper, which aligned to the markers in the silicon and measured the coordinates of the surface markers. The offset vector was then calculated as the difference between measured and target position (see Fig. 3C).
The wafer stepper successfully detects and aligns to markers at both 30 μm and 80 μm below the surface plane of the wafer. Subsequently, the wafer stepper successfully exposes new markers in focus at the wafer surface and detects these markers post-development. Analysis of the amplitude of the offset shows that it increases from an average of 14 ± 5 nm for a reference wafer to an average of 62 ± 8 nm for the 80 μm device layer (see online Supplementary Fig. S3). However, per wafer the spread in offset is large, with standard deviations up to 60 nm. A detailed analysis per wafer reveals that the offset amplitude increases with radial position of the marker (see online Supplementary  Fig. S4). For the control wafer, the offset amplitude increases from a few nm to < 25 nm with increasing radial position from center (0 mm) to the edge (60 mm). For the 80 μm thick device layers the offset amplitude increases from 20 nm to nearly 160 nm with increasing radial position. The dependence of offset amplitude on layer thickness and radial position could be due to wafer-stage positioning inaccuracies (specified at 0.08 μm) or projection inaccuracies resulting from nonflatness of the thick-polymeric layer. Nonetheless, this offset for thick device layers only increases by a factor of 2 compared to the wafer stage positioning accuracy or by a factor of 5 when compared to the control wafer. This performance is better than conventional back side alignment (2-3 μm offset) and at par with commercial state-of-the-art waferbonding systems (< 0.5 μm) [10]. This would be sufficiently small for many MEMS applications, while enabling compatibility with CMOS applications, where offsets < 0.5 μm are required.
Reduction of the offset error, especially for devices patterned at large radial positions, might be possible by determining possible systemic errors. A model might be derived from an analysis of the components of the offset as a function of the radial location. This analysis Fig. 4. Vector plots of offsets across the wafer reveal that the offsets are towards the center of the wafer with an amplitude of < 25 nm for the control wafer (A) and < 160 nm for wafers with an 80 μm device layer (B). Plotting the x-and y-components as function of the x-axis value and y-axis value respectively shows an inverse correlation, but with large spread for both the control wafer (C) and the wafer with 80 μm device layers (D). Error bars indicate 1σ standard deviation. reveals that the offsets, both for control wafer and for wafers with 80 um terrace, are in the direction of the wafer center, see Fig. 4A,B. The x and y components of the offset appear to be inversely proportional with respectively the x and y axis of the wafer, see Fig. 4C,D. Correcting a projection by subtracting an average offset of a certain radial position would be most practical. The spread in offset is large across the wafer compared to the average offset for radii < 30 mm. Thus, for images with coordinates < |30| mm correcting a projection with the average offset will not necessarily improve the alignment. However, for images with coordinates |60| mm radius, the spread in the offset component is much smaller than the average, so correcting a projection with this average will improve the alignment. Alternatively, to fully minimize the offset, a database could be setup for each wafer in which the offset per image is stored for subsequent lithography steps. Hence, these two methods could be applied to further reduce offsets if necessary.

Conclusions
This work developed an easily accessible and cost-efficient process for alignment of patterns on thick device layers to cavity patterns in handle layers of pre-fabricated cavity SOI wafers. The process was implemented for an ASML PAS5500-stepper and does not involve any special lithography or alignment equipment. The process involves patterning alignment markers to the wafer edge of the handle layer and utilizing a wafer-edge terracing process to reveal them after bonding the SOI wafer. The standard alignment system of the employed wafer stepper successfully detected these markers. Subsequent successful patterning of secondary alignment markers on wafers with different device layer thicknesses, mimicked using polymeric layers of 30 μm and 80 μm thickness, demonstrated the feasibility of this approach. Quantification of the offset due to out-of-plane alignment and image projection revealed an increase in offset amplitude from < 25 nm for control wafers to < 160 nm for wafers with 80 μm thick device layers. The offsets are towards the center of the wafer and are largest for radial positions bigger than 30 mm. Although the offsets are small enough for most MEMS applications, correction of offsets could be possible. This could be achieved by determining the average offset at large radii, or by storing all offset values in a per-wafer database, and correcting image projections with these values.
This novel alignment process is feasible with standard cleanroom equipment, while providing alignment performance at par with stateof-the-art wafer bonding technologies. c-SOI wafers could be sourced from commercial SOI suppliers that offer c-SOI products, and then be further processed in-house. In-house, the presented alignment process may be incorporated into CMOS, MEMS and NEMS technologies. This could enable the development of advanced thick cavity-based MEMS devices, potentially leading to novel, highly integrated, and more costeffective (bio) microsystems and microdevices.