Impact of single-defects on the variability of CMOS inverter circuits

Variations in the operational behavior of seemingly identical transistors pose a remarkable challenge for application engineers as integrated circuits have to be designed to be resilient against process and aging-related error sources. In small-area transistors, electrically active defects give rise to considerable device-to-device variations for instance of the threshold voltage. With the ongoing reduction of device dimensions, the impact of a single-defect becomes more and more relevant for the device behavior. While in circuit simulations, typically changes of mean values are considered, we thoroughly investigate the impact of variations of defect distributions on the signal propagation delay of an inverter circuit from the perspective of single oxide and interface defects. For this, the charge trapping kinetics of each defect is described using our stochastic charge trapping model. The impact of these single defects on the device behavior is extracted from detailed experimental studies. We demonstrate that the variation of the defect distributions between devices can lead to a signal propagation delay of several picoseconds for an inverter circuit. This can become a critical issue for circuits employing nanoscale transistors intended to operate at several hundreds of megahertz.


Introduction
The well-defined interplay of many different electronic devices determines the proper functionality and robustness of complex integrated electronic circuits. To ensure stable operation of such circuits, simulations employing compact models describing the behavior of the components are typically performed during the design process using SPICE tools. The compact models often rely on mean values for the characteristic electrical parameters, e.g. the threshold voltage, of a transistor [1][2][3]. However, in several simulation approaches also device-to-device variations are considered [4]. Instead of developing a full SPICE model which accounts for parameter variation, the combination of TCAD device simulations in conjunction with SPICE simulations is often used. For instance from TCAD simulations, the variability of the parameters of a transistor can be extracted and afterwards be considered to evaluate the variation of the circuit behavior employing a SPICE simulator [5].

Reliability aware circuit simulation
Two aging mechanisms have to be considered when designing an integrated circuit, hot-carrier degradation and bias temperature instabilities (BTI). I addition, process variations give rise to unexpected failure of circuits and components.
To consider for instance BTI, power-law-like models are often used to describe the observed change of a transistor's threshold voltage during operation [8]. By entering the nanoscale regime, single charge transitions become visible in the experimental data taken from nMOS and pMOS devices [9][10][11][12]. Consequently, the behavior of scaled devices cannot be solely described by a simple power-law function. Note that the impact of a defect on the device threshold voltage scales inversely with the device area. Thus, device-to-device variations are considerably more significant in scaled technologies than for their large-area counterparts, which emphasizes the importance of an accurate stochastic description of an entire technology's behavior [13,14].
In the recent past, considerable attention had been put on investigating single defects in small-area devices, primarily by thoroughly studying random telegraph noise [15][16][17], but also by employing the time-dependent defect spectroscopy [18][19][20][21]. By doing so, many peculiarities, like fixed versus switching trap behavior [22] or volatility of defects [23] have been observed. To model the charge trapping kinetics of defects observed from various technologies the non-radiative multiphonon model has been proposed and successfully applied [18,24]. Next to the charge capture and charge emission time, the impact of a defect on the device threshold voltage is statistically distributed, e.g. due to random variations of the dopant and defect distributions [25]. The average step height caused by defects has been evaluated by creating the complementary cumulative distribution function (CDF) of step-heights caused by charge emission events of single defects [13,26]. Initially, it has been observed that the complementary CDF follows a uni-modal exponential behavior for devices with a single insulating layer and a bi-modal exponential behavior for high-k gate stacks [13,20]. However, recent more detailed investigations have revealed that also for various SiON technologies, the complementary CDF exhibits two branches [27,28]. It has been further shown that the real impact of a defect on the threshold voltage is considerably larger than predicted by the charge sheet approximation (CSA) [27,28], which is, however, the commonly used estimator for the step-height in simulation tools [7].
To precisely evaluate the influence of the device-to-device variation caused by single defects, we use our defect simulator Comphy [7] to calculate the variations in the threshold voltage and employ the opensource SPICE simulator ngspice to study the consequences for electronic circuits. It has to be noted that established transistor models which are directly available in circuit simulators typically neglect the recovery of the device ΔV th at low gate-source bias [29,30]. As a consequence, the values predicted by these tools are expected to seriously overestimate the ΔV th behavior and thus could introduce overhead in the circuitry, which could be avoided otherwise. One way to circumvent the lack in the accuracy of the employed compact models is to consider the recovery behavior in a post-processing step [31]. In our simulations, we follow a similar approach to calculate the impact of the analog signals on the device threshold voltage. Our results show that when recovery is considered, a significantly lower degradation compared to the recovery-free simulations is obtained.

Calibration of the simulation tools
In our study, we consider the inverter circuit shown in Fig. 1. It can be seen that one of the two transistors is always in stress-mode (high applied gate bias), either positive BTI (PBTI) for the nMOS or negative BTI (NBTI) for the pMOS transistor. At the same time, the other transistor is in recovery-mode (zero gate-source bias). The subsequent application of stress and recovery phases to the transistors lead to altering of the threshold voltage of each of the devices which is determined by the corresponding charge trapping kinetics of a number of defects, see Fig. 2, and the corresponding macroscopic ΔV th degradation as shown in Fig. 3. Each of the defects can become charged or discharge during operation, depending on the applied bias patterns.
To calibrate Comphy and to determine the defect parameters, a large set of extended measure-stress-measure (eMSM) experiments at various electrical stress/recovery fields and times and different temperatures are required for pMOS and nMOS devices [32]. From the measurements made on large-area devices, as shown in Fig. 3, trap-bands can be extracted, which enable accurate calculation of the device threshold voltage drift ΔV th under arbitrary operating conditions, i.e. applied bias signals and temperature. Note that the extraction of the trap parameters can be dealt with in a semi-automatic fashion using our novel effective single defect decomposition (ESiD) extraction based on a non-negative least square estimator [6].
Next, the MSM scheme is applied to small-area devices of the same SiON technology. In nanoscale devices the experimental ΔV th data exhibits discrete steps, representing charge transition events of single defects, as visible in Fig. 4. The results are consistent with the data for the large-area counterparts from Fig. 3, where the pMOS devices show a larger drift of the ΔV th compared to the nMOS data. From this one might conclude that NBTI is more important than PBTI in circuit simulations. However, as we will see later, for the inverter circuit, PBTI can compensate for the signal propagation delay caused by NBTI, and thus leads to an improvement of the circuit degradation.
In small-area devices, the contributions of each of the defects to the total device degradation can be studied individually and can be statistically analyzed by calculating the complementary CDF, see Fig. 5.
For our devices, we observe a bi-modal and uni-modal exponential step-height distributions for nMOS and pMOS devices, respectively. Note that the maximum ΔV th caused by a single defect according to the CSA is around 0.2 mV, which is more than a factor of two smaller than what is extracted from the experimental data for the pMOS and nMOS transistors. To replicate the real impact of the single-defects on ΔV th , we have implemented a suitable model to Comphy to randomly draw defect distributions according to the measured complementary CDFs. This enables us to calculate the recovery behavior of the nanoscale devices, see Fig. 6. We observe an excellent agreement between the simulation results and the measurement data, which indicates the high accuracy of Fig. 1. (left) The circuit diagram of a CMOS inverter circuit is shown together with (right) the corresponding input and output bias signals. As can be seen, one of the transistors is always under stress, while at the other, no gate-source bias is applied. As demonstrated in this work, the device stress can alter the characteristics of the device, which leads to additional propagation delays of integrated circuits.  [6] for the investigated SiON technology are schematically shown in the band diagram of a representative pMOS transistor. Instead of considering an abrupt transition region between the channel and the insulator, a gradual transition of the bands is considered in our defect simulator [7]. By applying our toolset to measurestress measure sequences, defect distributions, i.e. trap levels, positions, and relaxation energies, can be extracted from the experimental data.
the reliability simulations and toolset.
Next to the contribution of a single trap to the overall ΔV th the trap depth and trap level are additional crucial parameters of our model. Especially a good agreement of these parameters with values from theoretical studies is a strong indicator for the physical soundness of the extracted trap distributions. As for CMOS inverters both nMOS and pMOS transistors are important, our model has to be able to replicate the behavior of both electron traps that determine the ΔV th characteristics of nMOS devices and hole traps that are dominant in pMOS transistors. While the electron traps are modeled to reside close to the conduction band edge of an nMOS transistor, the hole traps are considered to be located near the valence band edge of the pMOS counterpart [6]. It has to be noted that the trap levels of the defects used in our study are in good agreement with recent DFT calculations. There it has been discussed that the oxygen vacancy is a good candidate for an electron trapping site [33,34], while hydrogen-related defects, such as the hydroxyl-E' center, are likely candidates for hole traps [23,24].  3. A typical measure-stress-measure (MSM) sequence recorded on an nMOS transistor (blue) and a pMOS transistor (red) with W × L=10 × 10 after PBTI, and NBTI stress has been applied, respectively, is shown. The measurement series (symbols) has been recorded at T=100 • C and is measured without any interrupt. The stress conditions are indicated in the Figure and the recovery bias has been selected using a constant current criteria, i.e. V G to achieve I DS = ± 500 nA for the nMOS and pMOS devices. It can be observed that the pMOS device exhibits a considerably larger drift of the threshold voltage ΔV th , even though the same electric oxide field has been applied to the devices during stress. Our simulations (lines) nicely explains the experimental data. Note that single MSM sequences are not sufficient for the accurate extraction of the defect band properties, but rather a series of measurements has to be performed at various temperatures and bias conditions. Further experimental details and a novel methodology to efficiently extract common trap properties for the entire technology considered here are given in [6]. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.) Fig. 4. Contrary to large-area devices, in nanoscale transistors, discrete steps can be observed for nMOS (blue) and pMOS (red) transistors when stressrecovery measurements are performed. Each of the steps corresponds to a charge transition event of a single-defect, giving rise to a shift of the device threshold voltage. Even more significant is the variation in the transient behavior of ΔV th . This variation stems from the different charge trapping kinetics of the individual defects in the device. Additional variation is introduced due to different step-heights of electrically active defects and becomes even more severe in more scaled devices, i.e. scales inversely with active gate area [13]. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)

Fig. 5.
The complementary CDF has been extracted from the recovery traces from Fig. 4 for both nMOS and pMOS SiON transistors (symbols). To investigate the device-to-device variations induced by the defects, we make use of these distributions for the selection of the step-heights of the defects instead of applying the commonly used charge sheet approximation CSA. The values for η r are referred to the CSA by η r = η/η CSA with η CSA = ε 0 ε r A/d. As can be seen, with the CSA the impact of the defects on the ΔV th is considerably underestimated [28].

Analog AC signal simulations
With the calibrated reliability tools at hand, we simulate the aging of the transistors when AC patterns are applied to the inverter circuit, see Fig. 7. As can be seen, the device degradation is on the order of several μV, when a total signal time of 0.1 is simulated. Note that when the recovery of the devices is neglected, a considerably larger is obtained, which would lead to an overestimation of the degradation of the circuit. For the simulations, 100 points per period of the AC signal have been computed to ensure high accuracy of the obtained ΔV th . Also the transitions between low and high gate bias are simulated with t r = t f =10 to consider the dynamic behavior of the defects. At each simulation time step, the charge transition rates have to be evaluated for several hundreds of defects, and thus simulating long AC signals becomes computational inefficient.
An efficient approach has been developed in [35][36][37] where the ΔV th obtained after N periods of the AC signal can be calculated from the change of the defect occupancy during the first period of the AC signal. With this method, the device threshold voltage degradation can be calculated even for very long AC patterns, see Fig. 8. Again, a very small ΔV th can be observed for short stress times, but a considerable ΔV th becomes visible for nMOS and pMOS devices when the operational time exceeds 1 ks. It can also be seen that the behavior is significantly affected by the statistical distribution of trap parameters. For both nMOS and pMOS devices, a considerable variation of the transient ΔV th can be observed, which is further responsible for a significant variability in the signal propagation delay of the inverter circuit.

Results
A characteristic parameter of an inverter circuit is the signal propagation delay t D . It is defined as the time difference when the output and input signal is equal to V DD /2, see Fig. 9. To calculate the t D , we consider the threshold voltage of the transistors distributed according to the variation observed in Fig. 8 and perform a transient simulation using NGSPICE. In the final analysis step, we focus on the impact of the considerable variation of the device threshold voltage drift caused by different distributions for the step heights of the defects in Fig. 5. The resulting values for signal propagation delay of the CMOS inverter t D are summarized in Fig. 10, and are shown together with the individual contributions of the nMOS and pMOS devices to it. Considering the variability (black symbols), one can see that at short AC signal times, only a small variation can be observed for t D , as most of the defects in the transistor are still in their initial charge state. However, at long operation times, a large ensemble of defects has become charged, and as a result, a considerable variation in t D can be observed. The second aspect, i.e., the reliability of the inverter circuit, can be evaluated by considering the drift of t D over AC signal time. This is calculated as the average of the t D values extracted for nMOS and pMOS devices at the different time steps. It can be seen that as the ΔV th for pMOS devices dominates over nMOS devices, the evolution of is mainly determined by the pMOS transistor. This follows from the fact that charge trapping in nMOS and pMOS devices leads to a different sign of the obtained t D , which causes that BTI in both kinds of devices counteracts each other in terms of the t D of the can be observed, which is lower than for the pMOS transistors. In both cases, the degradation is calculated to be dramatically larger when recovery is neglected (dashed line). This emphasizes once more the importance of an accurate charge trapping model for circuit simulations. Note that direct calculation of the ΔV th response is computationally very demanding and thus not suitable for the evaluation of long stress series considering AC signals. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.) Fig. 8. Device-to-device variation and average device degradation of an AC pattern applied to nMOS (top) and pMOS (bottom) transistors. For the variation simulations, 100 trap distributions have been drawn according to the measured complementary CDF. A remarkable variation in the device behavior can be observed, which unavoidably leads to a variation of the signal propagation delay. Also shown here is the evolution of ΔV th when device recovery is omitted, which leads to a twice as high ΔV th , especially at high device operational times. Fig. 9. The propagation delay is the time difference between the input and output signal when 50% of V DD is reached. Note that in this schematic the timezero t D is positive, but in the case of matched transistors with an equal threshold voltage t D would be zero. As we are entirely focusing on the impact of the defect distribution on the impact of t D the V th of the selected devices will not affect our results.
inverter. Thus, the overall t D of the inverter circuit is smaller than the t D introduced by the degradation of the pMOS devices only. Both the absolute value of the propagation delay and its significant variation can be on the order of several ps, and thus can result in a serious concern for circuits operating at several hundreds of MHz.
In summary, the accurate description of the charge trapping kinetics and the replication of the real step height distribution are of utmost importance for simulations to correctly estimate reliability and variability issues in electronic circuits. We found the variation of signal propagation delay caused by different defect distributions of seemingly identical devices is on the range of up to 10 ps for the investigated technology. Note that for technologies employing devices with geometries of a few tens of nanometers, device-to-device variations are more severe and will thus lead to more significant delays of inverter circuits.

Conclusions
Our study examines the impact of single-defects on the signal propagation delay of inverter circuits when an AC signal is applied. For the inverter, we consider small-area MOS transistors of the same SiON technology. We demonstrate the importance of the recovery behavior of each of the transistors, as otherwise an overly pessimistic device degradation would be obtained. Another important feature is the distribution of the step-heights of the defects, i.e. their impact on the drift of the threshold voltage. Typically statistically distributed step heights are not considered in circuit simulations. Furthermore, the step heights are typically underestimated by a factor of more than two by the charge sheet approximation, which is mostly used in simulators. We employ a suitable model for the distributions of the step-heights of the defects and evaluate their impact on the signal propagation delay of an inverter circuit. Our results indicate with the drawn trap distribution, additional delays up to 10 ps are introduced at large operational times. This can be a severe concern for the interplay of circuit components at operating frequencies of several hundreds of MHz.

Declaration of competing interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper. Fig. 10. The signal propagation delay of the CMOS inverter t D is shown over the AC signal time. For each transistor, i.e. different trap distributions, leading to the recovery traces in 6 the resulting t D has been calculated for AC operating conditions (black symbols). It can be seen that variations in the single-defect distributions cause a considerable distribution in t D . The solid lines show the average t D extracted from 100 distributions per time step. Quite interestingly, while charge trapping at nMOS devices leads to a positive t D defects in pMOS transistors give rise to a negative t D and thus counteract the degradation introduced by the other device kind. As can also be seen, the majority of t D is caused by charge trapping in pMOS transistors. This is because the electron traps exhibit shorter trapping kinetics and thus can follow the dynamics of the AC signal. The hole traps that reside in the pMOS exhibit, on average larger emission times and thus lead to a build-up of t D . It has further to be noted that, even at short total operational times of a circuit in the order of several tens of ks the variation of the defect distributions among small-area devices of the same technology can introduce an additional signal propagation delay t D of several ps. While small variations may be negligible for AC signals in the 1 MHz range, considering the influence of the single-defects on t D can become particularly important for operating frequencies in the order of several hundreds of MHz or the GHz range.