Separation of electron and hole trapping components of PBTI in SiON nMOS transistors

In nMOS transistors the impact of positive bias temperature instability (PBTI) on the device performance is typically considered negligible and has thus been barely studied in the past. However, an accurate description of this phenomena requires and in depth understanding of the physical origin being responsible for the change of the device characteristics over time. For the assessment of PBTI in nanoscale SiON nMOS transistors we make use of the time-dependent defect spectroscopy (TDDS) and examine the device performance degradation at the single-defect level. Contrary to what is visible in large-area devices, our investigations clearly reveal that charge trapping at both electron and hole traps contributes to the overall drift of the threshold voltage in these devices. Furthermore we observe that hole traps account for around 20% of the total threshold voltage drift. To evaluate the impact of single-defects on the device performance we characterize the charge trapping kinetics of a number of defects, which can be explained by employing a two-state defect model. In our approach we observe charge trapping due to defect/channel interaction for electron traps and defect/gate interaction for hole traps. The extracted trap levels and trap depths clearly reveal that the electrically active electron traps reside closer to the SiON/Si interface while the hole traps are located closer to the poly-Si/SiON interface. Finally, the extracted trap parameters are fully consistent with defect candidates for electron and hole trapping from DFT calculations.


Introduction
The fast progress in microelectronics has resulted in a continuation of device scaling into the nano-meter regime. Next to the device geometry, the gate insulator layer used in metal-oxide semiconductor transistors (MOSFETs) has been scaled as well. In order to investigate the reliable operation of MOS devices, different measurement methods like stress-IV measurements [1], on-the-fly measurements [2], measurestress-measure (MSM) experiments [3] and noise measurements [4] are among others often applied. Many of the experiments aim at investigating the so-called bias temperature instability (BTI), which manifests itself as a drift of the threshold voltage over time [3,5]. In general BTI can be classified into positive BTI (PBTI) and negative BTI (NBTI), where the terms positive and negative refer to the sign of the gate bias. The origin of the observed drift of the threshold voltage lies in charging and discharging events of defects located at the semiconductor/insulator interface or of defects located inside the oxide. Next to charge trapping at existing defects, new defects can become created during device operation even at nominal bias conditions. In large-area MOSFETs, a number of such defects exists and their interaction with the carrier reservoirs, i.e. the channel and/or the gate, results in a continuous drift of the threshold voltage over time when MSM measurements are performed [6]. However, in nanoscale devices where only a handful of defects are present, charge transitions of individual defects are discrete steps in the corresponding measurement data revealing the physical origin of charge trapping more closely [3,7]. This makes it possible to elaborately study the contributions of electron and hole traps. In large-area nMOS devices, however, the individual contributions canceled out each other, and thus only a very weak average impact of BTI on the device threshold voltage can be observed.
So far, a large number of single-defect studies have been performed considering NBTI in devices employing SiON or SiO 2 as gate insulator [3,[8][9][10][11][12][13][14][15][16]. However, only little attention has been paid to PBTI in nMOS device since in pMOS devices the active defect density is approximately 10 times larger than in nMOS [7], BTI is typically considered more important for pMOS transistors. Nevertheless, for CMOS applications BTI of both device types is of significant importance, and the understanding of the physical origin of charge trapping in these devices is vital for further optimization of devices and circuits. Furthermore, it appears to be reasonable to assume the same defects are present in nMOS and pMOS devices and are triggered in a different way due to different positions of the Fermi levels in the channel and gate. As a consequence, after studying the response of these defects under as many different bias and temperature conditions as possible is important to https://doi.org/10.1016/j.microrel.2020.113746 Received 27 May 2020; Accepted 2 July 2020 improve our understanding of their behavior. Critical questions in this regard are the magnitude of the trap density, the impact of a defect on the overall device performance, and also the trap polarity, trap distribution and the trap levels. The most accurate way to answer these questions is by performing a detailed single-defect study employing nanoscale nMOS devices to provide the missing information.

Experimental
In this work, planar SiON n-channel MOSFETs with W = 90 nm, L = 70 nm, and an EOT = 2.2 nm are studied using time-dependent defect spectroscopy (TDDS applied to the gate while the drain-source current at V DS r = 100 mV is recorded at the same time. Afterwards, the recorded source current is converted to a threshold voltage shift and the recovery behavior is analyzed [17,18]. In contrast to large-area devices, the recovery in nanoscale transistors after PBTI stress proceeds in a discrete manner, see Fig. 1. The recovery traces are typically given in terms of an equivalent shift of the threshold voltage ΔV th , which is obtained from the measured drain current using an initial I D (V G ) curve. To achieve highest measurement resolution for single charge transitions of ΔV th < 1 mV an optimized defect probing instrument [5] has been used. This enables to observe a number of electron emission events ( Fig. 1 (left)), but quite remarkably also a significant number of hole traps with steps in the opposite (positive) direction, see Fig. 1 (middle). In contrast, no electron emission events are visible in the recovery traces measured on pMOS devices of similar geometry, see Fig. 1 (right). While the lack of observable electron trapping in pMOS devices may be due to the higher noise level, the presence of electron and hole trapping in nMOS devices signifies an important difference between NBTI and PBTI.

Defect distribution function
To study the relative contribution of electron and hole trapping to the total threshold voltage shift ΔV th , the complementary cumulative distribution functions (CCDFs) of the step heights of 79 nMOS transistors of the same technology is evaluated, see Fig. 2. The shown CCDF can be approximated by a bi-modal exponential distribution as with A 1, 2 = N T1, 2 × n T /n d being the product of the trap number per device N T and the ratio between the overall number of traps n T and the number of devices n d . η 1,2 denotes the mean contribution of a single charge capture/emission event [6,15,16,19]. In the following, the bimodality of the CCDF is separated into two (nearly) uni-modal distributions, which can be attributed to hole and electron traps. The resulting partial distributions show that on average hole traps have smaller step heights than electron traps indicating that they are further away from the channel. Considering the trap density, a remarkable number of 106 defects (38%) are identified as hole traps among a total of 266 traps.
The absolute contribution of hole trapping to the total threshold voltage shift ΔV th is calculated by with the step heights of the single hole/electron emission events d h i and d e i , respectively, and is analyzed in Fig. 3. It can be observed that hole trapping decreases the total ΔV th by about 22% for the bias and temperature conditions used here, while the fraction of hole traps is around 40%. These finding suggests that hole trapping plays an important role in the context of PBTI.
Of further interest is that the significantly smaller step heights for hole traps compared to electron traps observed from the CCDFs, give rise to the assumption that hole traps might be located at a larger distance from the channel than electron traps. To settle this question the

Single defects
In order to study the bias and temperature dependence of the charge capture and emission times, of single-defects we employ the TDDS [9]. Using TDDS the charge capture and emission times can be extracted under various bias conditions from a number of defects. To extract the charge emission time, stress (V DS = 0 V, V G = V G s ) and recovery cycles are repeatedly applied, and the recovery behavior is measured. During one measurement series, typically 100 traces are recorded at the same bias and temperature. Afterwards the discrete steps of the ΔV th transients are extracted and plotted as a distribution of the emission time versus their step heights (τ e , d). Such graphs are called spectral maps, see Fig. 4

(bottom).
After collecting all emission events from repeated stress/recovery measurements at constant biases and temperature, the single charge emission events form clusters in the spectral maps. Each cluster serves as a fingerprint for one individual defect. The intensity of a cluster is directly proportional to the number of emission events contributing to it. Furthermore, the number of capture and emission events is correlated because the charge has to be captured during stress phase first for emission to occur. Thus, the higher the ratio between the stress time and the average capture time of the defect is, the larger the probability of the defect to capture a charge during stress becomes. Finally, the vertical positions of the clusters in the spectral maps reflect the contribution of the single defects to total ΔV th at certain bias conditions and temperatures. From the spectral maps the emission time is calculated as the average of all single emission events of a certain defect.
In one of the DUTs we identified three electron traps, i.e. traps with negative step heights (Fig. 5). As can be seen, the defects #e1 and #e2 reduce their emission time by approximately 50% while defect #e3 moves into the measurement window defined by the recovery time t r = 10 s. On another device we observed two hole traps with a positive step height (Fig. 6). Similarly to the electron traps, the hole trap emission time also decreases with higher temperature. This observation confirms previous findings that both electron and hole trapping are temperature-activated processes [9,15,16,20].
Also in agreement with reports on NBTI on pMOS transistors, the probability of a defect to capture a charge during stress increases with higher stress voltage and stress time. This allows the extraction of the characteristic capture time for a hole/electron defect using the relation with the number of traces k and the number of emission events k e [3,7,9].

Results
In the following we evaluate the trap depth and trap levels of our defects. Previous reports have demonstrated that there is a direct correlation between the average contribution of traps to ΔV th and the trap depth (η ∝ x T ) [15,16,21]. However, from TDDS experiments it has been observed that defects can change their contribution to the threshold voltage shift when the device electrostatics at which the recovery is recorded changes [15,16,22]. As such, the step height alone is not a reliable indicator for the trap depth. To achieve an accurate estimate for   the trap position inside the band diagram we evaluate the charge trapping kinetics of three hole traps (Fig. 7) and nine electron traps (Fig. 8) extracted from our extensive measurements. To explain the charge capture and emission time characteristics we employ a two-state NMP defect model [23][24][25][26]. Considering this model the charge capture and emission time can be expressed by with the prefactor k c, e 0 and the energy barrier ΔE c,e for charge capture and emission. A fundamental fact is that if the trap level equals the Fermi level of the respective carrier reservoir for charge trapping, i.e. E t = E F , the charge capture time equals the charge emission time. With the above expression at hand, the trap position can be estimated by [26].
with the oxide thickness t ox and q 0 the elementary charge. Furthermore, the trap level can be calculated using [26] = where V Gi denotes the gate bias of the intersection point of the charge transition rates, e.g. V Gi = V G where τ c = τ e . It has to be noted that a two-state trapping model has been recently used to provide a consistent explanation for charge trapping in various technologies [26,27]. The estimated trap positions and trap levels for the analyzed traps are collected in the band diagram in Fig. 9. A necessary condition for a defect to contribute to ΔV th is that the defect must be energetically located in the so called active energy region (AER) for charge trapping. In general, defects below the Fermi level of a certain carrier reservoir, e.g. the Fermi level of the channel and the poly-gate in our MOSFETs, Fig. 6. Similarly to the electron traps, the two hole traps #h1 and #h2 with positive step heights move towards lower emission times with increasing temperature. Defect #h1 is shifted out of the measurement window when the device temperature is increased by 70°C.   are charged and become uncharged once they are shifted above the Fermi level, provided that the bias is applied for a longer time larger than the charge capture and emission time of the respective defect. Thus, the bias used for the MSM measurements determines the energetic area spanned by the AER for charge exchange between the channel and the defects, but also between the poly-gate and the defects. As can be seen in Fig. 9 the trap levels of the evaluated defects lie all inside the AERs. While the positions of the electron traps are found to be closer to the channel, the hole traps tend to reside more closely to the poly-gate. Note that, in accordance with the defect model, the spatial position is mainly determined by the gate bias dependence of the charge capture time. The observation that hole traps with smaller step heights are found to be located at a larger distance from the channel is also fully consistent with the smaller average step height extracted from the CCDF of step heights.
Finally it is worth mentioning that the trap levels of our study are in good agreement with DFT calculations suggesting that the oxygen vacancy is a potential trap candidate for electron trapping [28,29], while hydrogen-related defects could be responsible for hole trapping [30,31].

Conclusion
By studying PBTI in SiON nMOS devices at the single-defect level we have observed electron traps in addition to a sizable number hole traps. Furthermore, we observe a bi-modal exponential step height distribution one mode corresponding to electron traps and the second one to hole traps. Our study reveals that at the used bias conditions about 40% of the observed defects are hole traps, which are responsible for about 20% of the overall device degradation. The involvement of both electron and hole traps is a significant difference to the NBTI case. To extract trap parameters, we study the charge trapping kinetics of a number of hole and electron traps, which we explain using a two-state model. The obtained trap parameters indicate that hole traps reside more likely in the middle of the insulator, while electron traps are more likely located near the channel. Finally, the calculated trap positions and trap levels for charge trapping in nMOS transistors, and are fully consistent with trap levels for electron traps and hole traps extracted from DFT calculations.

Declaration of competing interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.