Strength determination of high-power LED die using point-load and line-load tests
Highlights
► Strengths of LED die are tested by point-load test (PLT) and line-load test (LLT). ► Mechanism has been discussed and validated via these test results and analyses. ► Die strengths on chip surface failure are 1.48 GPa for PLT and 1.2 GPa for LLT. ► Die strengths on sapphire surface failure are 1.36 GPa for PLT and 0.64 GPa for LLT. ► Two tests have been found feasible, easy-to-use and reliable for LED die strength.
Introduction
High-power light emitting diodes (LEDs) have gradually gained popularity in many lighting applications today such as general illumination, automobile headlight and taillight, and backlighting in LCD displays and TVs. In these applications, the high-power LED dies could be subjected to mechanical, thermal, and environmental loads during packaging manufacturing processes (such as die bonding, wire bonding and encapsulation) and services. Therefore, the strength of LED dies, cut from the wafers after manufacturing processes (such as wafer grinding and laser dicing), has to be determined for the need to assure good design and reliability of the LED packages. In the literature, a ball-breaker test proposed by Hawkins et al. [1] was used to determine the strength of silicon die from the wafers after different grinding and polishing processes [2]. And further different test methods (including three-point bending, four-point bending and ball-breaker tests) [3] were evaluated for effectively determining the die strength. A ring-on-ring and four-point bending tests associated with Weibull probability analysis were employed for determining the die strength in an attempt to separate the surface grinding and edge dicing effects [4]. Recently, the geometry and sharpness of scratch tips for a few large and deep scratches created by wafer thinning process were found to significantly affect the strength data according to the three-point bending test results [5]. Two new test methods: the point-load test (PLT) and line-load test (LLT) have been proposed, and the silicon die strength has been determined [6], [7], [8]. It is found that there are four factors that influence the die strength: the surface conditions of the die (including grinding-mark direction and surface roughness), the edge crack of the die (so-called chipping created during the wafer sawing process), the weak plane of the crystal lattice of silicon, and, sometimes, the test methods with different loading types. Most recently, to precisely determine the die strength, the PLT has been reevaluated and improved by ANSYS analysis with contact-element models and the related formulation, which is associated with Hertzian contact theory [9]. However, from the literature, there is no report available on the determination of LED die strength. A typical high-power LED die with the size of 1 × 1 × 0.1 mm3 is so relatively tiny that the determination of the die strength by either convectional three-point bending, or four-point bending, or ring-on-ring tests would become very challenging and even impossible. Thus, this study aims to determine the strength of high-power LED dies by the PLTs with two different pin radii (0.063 mm and 0.25 mm), and LLT, associated with a plate-on-elastic-foundation configuration. The strength of the LED dies can be determined by these tests combined with ANSYS analyses, which are used to convert the die failure force into the die strength. Finally, an attempt is made to evaluate the factors that affect the variation of the die strength data after the tests.
Section snippets
Test methods and specimens
The test specimens of high-power LED dies are with a square plate-like configuration of 1 × 1 × 0.1 mm3 and with a few very thin layers of gallium nitride (GaN) grown on the top of a sapphire substrate, as shown in Fig. 1. Two-layer structure including the LED chip (with a group of GaN layers) and sapphire substrate is assumed and simplified for analyses of the test specimen in this study. The thickness ratio of the nitride layers and the sapphire substrate is less than 5%. The sapphire substrate
Determination of maximum die stress
To correlate the maximum failure force (Fmax), obtained from the PLT and LLT, with the die strength, the stress state of the die specimen is required and can be calculated through ANSYS analyses. Prior to these ANSYS analyses, the material properties (E and ν) of the elastic foundation must be precisely determined by ANSYS analyses associated with the previously mentioned experiments. For this calculation, the vertical displacement (δ) obtained by ANSYS has to be matched very well with the
Results and discussion
When the LED die specimens were loaded by the pin or line load at the central point on the sapphire surface (with the chip face-down specimen) for the PLT or LLT, the maximum tensile stress dominating failure occurs at the same point but on the opposite surface (chip surface) and vice versa. Fig. 6 shows the experimental results of average maximum force (Fmax) from the PLTs with rP = 0.063 mm and 0.25 mm, and LLT with c = 0.3 mm for failures on the chip surface (for the chip face-down specimen) and
Conclusions
The strength of high-power LED die with a size of 1 × 1 × 0.1 mm3 was successfully determined by point-load test (PLT) and line-load test (LLT) associated with ANSYS analyses. The ANSYS models of the PLT and LLT validated with experimental force–displacement curves provided the detailed stress distributions for further converting the die failure force obtained from both tests into the die strength. The mechanism of the tensile-stress dominating die strength has been discussed and validated in detail
References (10)
- et al.
Evaluation of test methods for silicon die strength
Microelectron Reliab
(2008) - Hawkins G, Berg H, Mahalingam M, Lewis G, Lofgran L. Measurement of silicon strength as affected by wafer back...
- et al.
Assessment of backside processes through die strength evaluation
IEEE Trans Adv Pack
(2000) - et al.
An overview of experimental methodologies and their applications die strength
IEEE Trans Adv Pack
(2003) - et al.
The strength of the silicon die in flip-chip assemblies
ASME J Electron Pack
(2003)
Cited by (1)
Geometric Nonlinear Effect on Biaxial Bending Strength of Thin Silicon Die in the PoEF Test
2020, IEEE Transactions on Device and Materials Reliability