Size effects on the DC characteristics and low frequency noise of double polysilicon NPN bipolar transistors
Introduction
Double-poly bipolar transistors are now widely used in high frequency analog processes [1], [2]. Due to their compatibility with CMOS technologies, they can be used in analog and mixed analog–digital high frequency applications. High unity gain frequency, up to 50 GHz, can be obtained since shallow base thicknesses as well as small active areas can be obtained [2]. Low frequency noise is an essential characteristic of such devices, both for low frequency preamplification and also for high frequency applications since low frequency noise can be upconverted through non-linearities (phase noise in oscillators, mixers) [3], [4]. Numerous papers have been devoted to the low frequency noise modelization and measurement in polysilicon emitter bipolar transistors. The noise spectrum is usually found to exhibit a 1/fγ (γ close to unity) dependency at low frequencies (<10 kHz) and is white at higher frequencies. The main source of 1/f noise is located at the monosilicon–polysilicon emitter interface [5], [6], [7], [8], [9], [10]. Furthermore, the noise density is generally found to vary as the inverse of the junction area [11], [12].
However, our investigations in sub-micronic structures showed unexpected geometrical dependencies, both for the low frequency excess noise as well as for the base and collector saturation currents. This paper deals with these unexpected geometrical dependencies observed both on the saturation current densities and 1/f noise level and their tentative modelization. This paper is organized as follows. Section 2 describes the devices used for these experiments and experimental techniques involved. Our measurement results are given in section 3. Finally, section 4 gives an analysis of these results.
Section snippets
Devices, measurements and parameter extraction
A simplified cross-section of the studied devices is shown in Fig. 1. After an epitaxial n doped monosilicon growth, a polysilicon layer is deposited and p doped by implantation. The monosilicon part of the transistor base is then realized via of an annealing process that diffuses p dopants into the monosilicon part of the base. An emitter opening, of length L and width W is defined by etching the polysilicon layer. The remaining polysilicon layer provides a low resistance access to the
Results
A typical Gummel plot of the studied devices is given in Fig. 2 and it indicates that the non-ideal base current is negligible for a collector current varying over a wide range. For 0.45 V < VBE < 0.85 V, the base current can thus be modeled by:A typical evolution of the power spectral density of current noise as a function of the frequency is also shown in Fig. 3 for different base currents. A 1/f dependency can be observed at low frequencies whereas the current noise spectral
Analysis
As usually found in polysilicon bipolar transistors [6], [14], [15], [16], [17], parameter Kf is roughly inversely proportional to the device active area (Fig. 4). The parameters JSB and the Kf × AE product are expected to be independent of the active area whereas Fig. 4, Fig. 5 clearly indicate some deviations, which have to be explained.
Fig. 6 presents the evolution of the base current noise spectral density versus the base current for each characterized geometries while Fig. 7, Fig. 8 show,
Conclusion
Unexpected geometrical dependencies have been found, affecting both DC and noise characteristics of double polysilicon bipolar transistors when the width of the emitter is close to the technology resolution. We proposed a model taking into account a variation of the interfacial oxide thickness at the periphery of the emitter, which is physically acceptable and which successfully models the base saturation current density and the low frequency noise.
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