Experimental verification of the effectiveness of a new circuit to mitigate single event upsets in a Xilinx Artix-7 field programmable gate array

Highlights

• An event upsets mitigation technique, which makes use of Dual Modular Redundancy (DMR) with a filter, was developed.

• It uses fewer resources than the widely used Triple Modular Redundancy (TMR) and significantly reduce event upsets in a FPGA.

• This paper describes the effectiveness of the DMR-Filter combination mitigation technique in reducing the likelihood of event upsets occurring in Xilinx's Artix-7 FPGA when exposed to highly accelerated particles, similar to those in space.

• This originality and contribution that this paper demonstrated was the effectiveness of a new mitigation technique in correcting errors that affect digital logic applications in SRAM FPGAs when exposed to highly accelerated particles, similar to those in space.

• Consequently, some SEU characterization of the Xilinx's Artix-7 SRAM FPGA was presented. This new approach of the SET mitigation in the user logic of SRAM FPGA's has shown an increase in the efficiency compared to unmitigated designs.

Abstract

A single event transient (SET) filtering technique for the Xilinx Artix-7 Field Programmable Gate Array (FPGA) is investigated experimentally. The technique combines AND – OR gate circuits to provide a single circuit that can dissipate SETs irrespective of whether the input state is high or low. It uses fewer resources than the widely used Triple Modular Redundancy (TMR) and significantly reduces event upsets in a FPGA.

This paper presents the results of the experimental investigation, with the SET filter applied to various sequential circuit configurations, by proton beam irradiation. Their implementation and evaluation in-beam show their efficiency in eliminating SETs and single event upsets (SEU) compared to unmitigated designs.

Introduction

Space technology has overcome numerous problems in the attempt to improve the overall efficiency of memory-based digital devices aboard satellites; one such problem is the mitigation of the negative effects of radiation [1]. Such radiation increases the risk of failure, and enormous costs are involved when designing and consequently deploying digital circuitry in space.

The field programmable gate array (FPGA) is one type advanced programmable logic device which has been used in space technology over the years [2]. For low volume production and prototyping applications, it compares better to Application-Specific Integrated Circuits (ASIC) in terms of design cycle time, re-programmability, cost and overall performance. Despite these inherent advantages, deployment of the FPGA in the space environment is still a challenge due to the existence of radiation originating from solar wind, particles trapped in the Van Allen belts and cosmic rays [3]. Exposure to radiation can lead to incorrect voltage levels, broadly known as single event effects (SEEs), in the logic circuitry of digital devices deployed in space [4].

SEEs are caused by ionization when a highly charged particle, such as a neutron, proton or heavy ion strikes a circuit element leading to incorrect logic values. Such effects can either be permanent or temporary, more commonly referred to as hard or soft errors, respectively [5]. The permanent effects include: Single event burn-out (SEB), single event gate rapture (SEGR) and single event latch-up (SEL), while some of the temporary effects include single event upsets (SEU) and single event transients (SET).

The unpredictable nature of the space environment calls for a lot of thought and consideration to be taken in the design process before deployment of digital devices in space. One such consideration is the need for effective techniques to mitigate the SEEs.

An alternative to mitigation techniques, is a process called radiation hardening (RH). This process involves changing the characteristics of the raw materials at the silicon component level, to withstand the harsh radiation environment of certain missions [6]. However, it is very expensive and not commercially viable, especially for research and deployment of smaller missions like Cube Satellites. In this regard, less costly redundant and filter mitigation techniques have been developed by researchers in the field, with great success [4].

The response of a particular family of FPGAs to SEUs, depends on the architecture of its configuration memory [7]. For example, SRAM FPGAs are a family of FPGAs which have configuration memory that consists of SRAM cells. It has been shown that the configuration memory of SRAM based FPGAs is sensitive to SEUs, which causes a bit flip, when struck by an energetic charged particle [8]. This results in a change in functionality.

Flash based FPGAs, on the other hand, have configuration memory that consists of Flash memory cells, which have been shown to be resistant to SEUs [9]. However, previous tests have shown that Flash FPGAs are sensitive to soft errors, or SETs, in the combinational user logic, and to SEUs in the sequential logic elements [10]. Therefore, in order to use Flash FPGAs in a radiation environment, the mitigation must be applied to the user logic, as well as the memory elements. It is for this reason that most studies on the SET characterization of FPGA's have been performed on Flash-Based FPGAs due to its configuration memory being resistant to SEU's. The few studies in the literature that refer to SET characterization in SRAM-based FPGAs are based on software and hardware simulations without using any radiation facility [11,12]. Therefore, they do not provide a quantitative measure for SET probability and severity of the phenomenon in the form of the SET cross section [13].

The focus of this paper is to present experimental evidence to demonstrate the effectiveness of a new mitigation technique in correcting errors that affect digital logic applications in SRAM FPGAs when exposed to highly accelerated particles, similar to those in space [14]. Consequently, some SEU characterization of the Xilinx's Artix-7 SRAM FPGA is also presented.