A modified asymmetric cascaded multilevel DC–AC converter with switched diodes using FPGA processor implementation
Introduction
As multi-level DC-AC converters have potential to generate waveforms with good harmonic range and voltage, they are getting increased attention. Many applications like AC power supplies, drive systems, power grid, and solar system uses multilevel DC-AC converter.
The multilevel commences from three levels. Total Harmonic Distortion of the output waveform draws near to zero, if the amount of levels extent to infinity. One of the important favours of multilevel configuration is without curtailing the output power of DC-AC converter it can reduce harmonics in the output waveform. But, the issues like voltage unbalance, requirement of voltage clamping, circuit packaging and design constraints limit the attainable voltage level.
Numerous traditional multilevel DC-AC converters is available out there. (i) Neutral Point Clamp (NPC) (ii) The Cascaded H-Bridge (CHB) (iii) The Flying Capacitor (FC) multilevel DC-AC converter [1], [2], [3]. Traditional multilevel DC-AC converters has unique demerits like high amount of switches for getting greater amount of output voltage levels that may demand excessive effort for the installation, the switching complexity, increased quantity of gate driver circuits and the size. Various multilevel DC-AC converter configurations brought together to curtail the switch count, gate drivers, dc sources and the voltage rating of the switches [4], [5], [6], [7], [8], [9]. Quite a few control methods studied to curtail the harmonics in output [10]. Pulse Width Modulation (PWM) is broadly in a job to regulate the DC–AC converter's output. PWM DC-AC converters are capable to regulate their output voltage and frequency together by carving the wave personalized to distinct needs of applications [11], [12], [13], [14]. And thereby can lessen the harmonic factors in output. These feature have made them strong contender in numerous power conversion systems.
In the know, there are many control methods, which are employed in multilevel DC–AC converters [15], [16], [17], [18], [19]. In particular, for Cascaded Multi level DC–AC converter hybrid modulation technique serve the demands [20], [21], [22].Hybrid modulation stands for the blend of Fundamental frequency PWM (FPWM) and Multi-level Sinusoidal PWM (MSPWM), in order that the output inherits reduction in switching loss from FPWM, and commendable harmonic characteristics from MSPWM. The cascaded multilevel DC–AC converter using capacitors, for voltage dividing, has difficulty in balancing the capacitor voltages [23]. And it demands more efforts to balance the capacitor voltages [24], [25], [26].Hence isolated DC sources can be a better choice.
When compared to symmetric multilevel DC–AC converters, asymmetric multilevel DC–AC converters are capable of producing greater amount of output levels using at most equal amount power electronic switches since isolated dc sources are distinct in values. Consequently the installation space and cost are comparatively low [27], [28].
In this paper, an asymmetric cascaded multilevel DC–AC converter configuration is proposed with a reduced amount of switches. This configuration is also able to produce the supreme quantity of output voltage levels by cascading and it is appropriate for high and medium power applications.
Section snippets
Proposed system
Fig. 1 introduces the generalized structure of the proposed asymmetric cascaded multilevel DC-AC converter. It comprises a low frequency DC–AC converter with switched diodes placed at the bottom and high frequency DC–AC converter placed at the top in cascade, in order to get required multi-level output. DC voltage sources vdc–2nvdc are independent to one another. The magnitude of the first voltage source of low frequency DC–AC converter is twice the high frequency DC–AC converter and each
Switching technique
In the proposed configuration, both high and low frequency switching signals are used. Minimum number of switches operated at high frequency and maximum number of switches operated at low frequency.
This minimizes the losses of switching. The hybrid modulation technique of the proposed converter configuration is described for fifteen levels. Switches PS5 and PS8 are driven by contrasting the reference wave R1 with carrier wave C. Switches PS6 and PS7 are switched by contrasting the reference
Losses calculation
The mean switching loss Psloss inside the switch produced all through the progress of switch is given by,
Where tc(on) and tc(off) stands for the switch on and switch off time intervals, correspondingly. For additional transparency, the proposed circuit with fifteen levels is weighed with the known and analogous configurations below. For generalization, the proposed method and also the familiar DC-AC converter circuits are expected to be functioned at the
Simulation results
The feasibility of the proposed topology is verified using MATLAB/SIMULINK. The simulation is done using the parameters and values as displayed in Table 4 with the switching algorithm stated in segment 3 and the same technique can be pushed to any necessary number of levels. Thus at high frequency, low voltage rated switches are operated and at fundamental frequency, high-voltage rated switches are operated. Generally high frequency switches are having low voltage rating comparatively and vice
Experimental results
The proposed cascaded multi-level DC–AC converter is prototyped using FPGA SPARTAN 6 through Xilinx and the hardware schematic organisation for fifteen level output voltage is shown in Fig 15. It has two different DC–AC converters in cascade. Both the DC–AC converters are operating at different frequency as the name suggests low frequency DC–AC converter and the high frequency DC–AC converter. The high frequency DC–AC converter is fitted out using a separate DC source which is of isolated type
Conclusion
In this paper, a modified asymmetric cascaded multilevel DC–AC converter structure is presented and a hybrid PWM strategy was designed and is upgraded into a new asymmetrical cascaded multilevel DC–AC converter structure. The proposed structure generates a 15 -level output voltage with minimum amount of switches. The proposed method proves that there is a substantial improvement in the sinusoidality by means of greater amount of output voltage level. Also this paper proposes a new approach,
Ethical approval
This article does not contain any studies with human participants or animals performed by any of the authors.
Declaration of Competing Interest
This paper has not communicated anywhere till this moment, now only it is communicated to your esteemed journal for the publication with the knowledge of all co-authors.
D. Arun Prasad graduated in Electrical and Electronics Engineering in 2006 from Anna University, Chennai,Tamilnadu, India and Post graduated in Power Electronics and Drives in 2011 from Anna University, Trichy, Tamilnadu, India. He is currently pursuing his Ph.D. in Power Electronics and Drives at Anna University, Chennai, Tamilnadu, India. His research interests include Multi-level inverters, switching strategies, and their applications. He is currently working as an Assistant Professor of
References (28)
- et al.
Symmetric and asymmetric multilevel inverter topologies with reduced switching devices
Elect. Power Syst. Res.
(2012) - et al.
Reduction of dc voltage sources and switches in asymmetrical multilevel converters using a novel topology
Elect. Power Syst. Res.
(2007) - et al.
Multilevel inverters: a survey of topologies, controls, and applications
IEEE Trans. Ind. Electron.
(2002) - et al.
A survey on neutral-point-clamped inverters
IEEE Trans. Ind. Electron.
(2010) - et al.
A survey on cascaded multilevel inverters
IEEE Trans. Ind. Electron.
(2010) - et al.
A single-phase cascaded multilevel inverter based on a new basic unit with reduced number of power switches
IEEE Trans. Ind. Electron.
(2015) - et al.
A new general topology for cascaded multilevel inverters with reduced number of components based on developed H-bridge
IEEE Trans. Ind. Electron.
(2014) - et al.
Performance evaluation of an asymmetrical reduced switched multi-level inverter for a grid-connected pv system
IET Renew. Power Gener.
(2018) - et al.
Symmetric switched diode multilevel inverter structure with minimised switch count
J Eng.
(2017) - et al.
Harmonic distortion in PWM inverter output waveforms
IEE Proc. B (Elect. Power Appl.)
(1987)
Voltage sharing converter to supply single-phase asymmetric four-level diode clamped inverter with high power factor loads
IEEE Trans. Power Electron.
Multilevel diode clamped converter for photovoltaic generators with independent voltage control of each solar array
IEEE Trans. Ind. Electron.
Multilevel inverter for interfacing renewable energy sources with low/medium- and high-voltage grids
IET Renew. Power Gener.
A simple capacitor voltage balancing scheme for the cascaded five-level inverter fed AC machine drive
Cited by (5)
Design of Hybrid Switched Diode Multilevel Inverter Using Single DC Source
2024, Journal of Electrical Engineering and TechnologyDesign of a 21-level multilevel inverter with minimum number of devices count
2023, International Journal of Circuit Theory and ApplicationsOptimal sliding mode converter with energy management system for hybrid electric vehicle
2021, Proceedings of the 2021 1st International Conference on Advances in Electrical, Computing, Communications and Sustainable Technologies, ICAECT 2021A new tapped sources stack succored modified HX bridge MLI
2020, Circuit World
D. Arun Prasad graduated in Electrical and Electronics Engineering in 2006 from Anna University, Chennai,Tamilnadu, India and Post graduated in Power Electronics and Drives in 2011 from Anna University, Trichy, Tamilnadu, India. He is currently pursuing his Ph.D. in Power Electronics and Drives at Anna University, Chennai, Tamilnadu, India. His research interests include Multi-level inverters, switching strategies, and their applications. He is currently working as an Assistant Professor of Department of Electrical and Electronics Engineering, PSNA College of Engineering and Technology, Dindigul, Tamil Nadu, India.
K. Mahadevan graduated in Electrical and Electronics Engineering in 1993 and Post graduated in Industrial Engineering in 1997 and PhD in 2006 from Madurai Kamaraj University, Tamilnadu, India. He has more than 22 years of teaching experience. He has published several papers in peer reviewed international journals of high reputed and has presented research papers in more than 35 national and international level conferences. His field of interest includes Electrical circuits, Electromagnetic Fields, Power system engineering and Optimization Techniques. He is currently working as a Professor of Electrical and Electronics Engineering, PSNA College of Engineering and Technology, Dindigul, India.
M. Arul Prasanna received his B.E. in Electrical and Electronics Engineering in 2006 and M.E. in Power Electronics and Drives in 2008 from Anna University, Chennai, Tamil Nadu, India. He received his Ph.D. from Anna University, Chennai, Tamil Nadu, India in 2015. His research interests include Power Electronics and Drives, Current Source Inverters, Embedded Automation, AC drives and their applications. He is currently working as an Associate Professor in the Department of Electrical and Electronics Engineering at the PSNA College of Engineering and Technology, Dindigul, Tamil Nadu, India.