M2DC – Modular Microserver DataCentre with heterogeneous hardware
Introduction
During the last decade, the fast development of compute-demanding applications such as Internet of Things, data analytics, media processing, and cloud platforms caused a fast growth of data centres, as illustrated by the latest Cisco Cloud Index report, which indicates that global data centre IP traffic is expected to nearly triple (2.8-fold) over the next 5 years. Overall, data centre IP traffic will grow at a compound annual growth rate (CAGR) of 23% from 2013 to 2018 [1]. This fast growth called for large investments and increased power usage. To cope with these issues without slowing down the innovation based on the adoption of pervasive computing technologies, dramatic decreases in costs and power requirements are needed. These decreases must be, however, accompanied by assured Quality of Service (QoS), high levels of reliability and security, and by ease of configuration, integration, and application execution, even if system improvements are achieved with the use of cutting-edge and specialized technologies [2]. At the same time, new technologies and embedded computing architectures create numerous new opportunities. New architectures with high computing power to power consumption ratios are becoming widely available, such as mobile processors (e.g., ARM-based multi/many-cores), embedded SoCs (System-on-Chip) including GPU or FPGA-based accelerators, etc. Going beyond the separation between embedded and desktop/server markets, these architectures draw a continuum of computing resources, ranging from small, power-optimized micro-controllers to large, powerful many-core server chips, enabling designers to tailor a system to the exact needs of applications and workload with appropriate components. These challenges and opportunities are at the heart of the Modular Microserver DataCentre (M2DC) project [3]. M2DC will capitalize on the European strength in embedded system design and it will leverage the opportunities offered by cutting-edge computing resources and technologies so as to build specialized energy-efficient appliances aiming at meeting the needs of future high-value applications, based on intensive media processing, IoT or even HPC.
To address these emerging challenges, M2DC will investigate, develop and demonstrate as a prototype in an operational environment a modular, highly-efficient, cost-optimized server architecture composed of heterogeneous microserver computing resources, being able to be tailored to meet requirements from different application domains such as image processing, IoT, cloud computing and HPC. M2DC will develop turnkey appliances based on a microserver system enabling to build use case driven, modular, high-density efficient data centres. The idea is to provide use cases in the form of turnkey appliances that can be easily configured, produced, installed and maintained. Thus, the main M2DC goal is to deliver a new class of appliances with the following properties:
- P1
Low cost – taking into account the whole appliance life cycle (purchase, operation, maintenance and refresh cycles) and the Total Cost of Ownership (TCO) optimisation;
- P2
Low power and high energy efficiency – dramatically reducing power usage and heat dissipation while meeting Quality of Service (QoS) for key and emerging applications;
- P3
Dependable by design – delivering built-in reliability and security by integrating fast and efficient monitoring and management functions,
- P4
Versatile and scalable – easy to customize and update (software and hardware) to specific application types and large scales by seamless inclusion of heterogeneous and highly parallel computing resources,
- P5
Easy to use and integrate with data centre ecosystems – easy provisioning, monitoring and management by modern DCIM (Data Centre Infrastructure Management), cloud and HPC software;
- P6
Applicable to a variety of real-life applications – facilitating application and middleware programming, deployment, and optimisation in order to use M2DC appliances for various important real-life applications such as Image Processing or Internet of Things data analytics.
To develop its appliances, M2DC proposes a flexible server architecture that can be easily customized, equipped with intelligent power management and integrated with well-defined interfaces to the surrounding software ecosystem. The server architecture is based on low power System on Chip (SoC) components accompanied by built-in enhancements (e.g. for performance acceleration, efficiency, dependability) at system level, thus delivering great efficiency while minimizing the effort needed from users. M2DC appliances will enable TCO optimization for specific use cases and application areas. The overall costs will be lowered by using low cost microserver modules, decreasing of energy consumption costs, and facilitating maintenance and integration with existing computing environments. The connections between this approach and M2DC appliance properties are illustrated in Fig. 1.
Organization of the paper. The rest of this paper is organized as follows. In Section 2, we provide an overview of the M2DC modular microserver hardware and software architecture, while in Section 3 we provide a more in-depth look at thermal management. In Section 4, we briefly describe the range of application scenarios on which the M2DC technology will be demonstrated, while in Section 5 we offer initial benchmarking results for the ARM Aarch64 architecture which will serve as the general purpose processor unit. Finally, in Section 6 we review some related works in previous European projects and in Section 7 we draw our conclusions.
Section snippets
Architecture overview
The M2DC project targets the development of a resource-efficient, highly scalable, modular microserver system that can be easily configured to fit the workload requirements of a wide variety of applications. Low-power microserver modules could be easily combined with reconfigurable and massively parallel hardware accelerators using a high-speed low-latency communication infrastructure to provide the heterogeneous mix of cutting edge technologies required by customers and applications.
Thermal management
Due to the heterogeneity, power density, and thus, possible thermal imbalance of the M2DC microserver, proper energy- and thermal-aware management becomes crucial not only in achieving significant energy savings, but in assuring the high reliability of the system. However, these management policies need to consider various challenges and conditions including workload fluctuations, power leakage, managing hot spots, and finding a trade-off between workload and resource management. To deal with
Use case scenarios
One of the key goals of the M2DC project is to deliver appliances well suited for specific classes of popular or emerging relevant applications. Thus, a crucial part of the strategy of the project is to steer the joint development of software and hardware by specific real-life use cases identified by the project partners. Such a continuous validation will enable M2DC to deliver optimized appliances customized to relevant and real-life workloads and use cases. The M2DC use cases have been
Initial benchmarking
In order to evaluate the performance of the M2DC systems, we have collected results from several standard benchmarking suites on our Aarch64 testbed machine and compared them against different Intel-based 64-bit servers.
With the idea of being as thorough as possible, we have selected three different benchmarking suites:
- •
LMbench [22]: A low level benchmark that measures machine characteristics such as process context switch, system call and IPC latencies as well as memory bandwidth and
Related works
To achieve its objectives, M2DC takes as baseline the results of different EU FP7 projects, to which some of the members of the M2DC participate.
FiPS [6], [26] results will be reused for the management of heterogeneity in a server infrastructure. In particular M2DC will take the RECS3.0 prototype currently under development as a direct basis for further enhancements, and the application mapping methodology will also be developed towards the goal of turnkey appliances. RECS3.0 is in turn based
Conclusions
We have presented an overview of M2DC, an EU H2020 project started in January 2016 and aimed at defining a modular microserver architecture for future data centres. M2DC aims at reducing TCO for selected applications and use cases by 50% compared to other servers. Depending on selected system configuration and application, it also improves energy-efficiency by 10–100 times, compared to 2013 typical servers.
To this end, M2DC proposes a flexible, high-density, cost-optimised server architecture
Acknowledgements
This work was supported in part by the European Union’s Horizon 2020 Research and Innovation Programme, under grant 688201, Modular Microserver DataCentre (M2DC).
Dr. Ariel Oleksiak works in the applications department at Poznan Supercomputing and Networking Center since 2002. He received his M.Sc. degree in computer science, intelligent decision support systems, from the Poznan University of Technology, Poland in 2001 and Ph.D. in computer science from the same institution in 2009. Since 2008 he has been a deputy head of the department and now leads an energy-efficiency technologies group. His research interests include mainly energy efficient
References (30)
- et al.
Monitoring fungal growth on brown rice grains using rapid and non-destructive hyperspectral imaging
Int. J. Food Microbiol.
(2015) - Cisco, Cisco Global Cloud Index: Forecast and Methodology 2013–2018 White Paper, 2014,...
- M. Duranton, K. D. Bosschere, A. Cohen, J. Maebe, H. Munk, The HiPEAC Vision 2015, 2015,...
- et al.
The m2dc project: modular microserver datacentre
2016 Euromicro Conference on Digital System Design (DSD)
(2016) - PICMG, PICMG COM.0 R2.1 - Com Express Module Base Specification, (Available at http://www.picmg.org). Accessed:...
- Toradex, Apalis Computer Module - Module Specification(Available at...
- et al.
A scalable server architecture for next-generation heterogeneous compute clusters
Proceedings of the 2014 12th IEEE International Conference on Embedded and Ubiquitous Computing
(2014) The self-organizing map
Proc. IEEE
(1990)- et al.
Practical application of self-organizing maps to interrelate biodiversity and functional data in NGS-based metagenomics
ISME J.
(2011) - et al.
A reconfigurable neuroprocessor for self-organizing feature maps
Neurocomputing
(2013)
Opencl performance portability for general-purpose computation on graphics processor units: an exploration on cryptographic primitives
Concurr. Comput.
Exploiting bit-level parallelism in GPGPUs: a case study on KeeLoq exhaustive search attacks
Record setting software implementation of DES using CUDA
SHA-3 Standard: Permutation-Based Hash and Extendable-Output Functions
FIPS Publication
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Dr. Ariel Oleksiak works in the applications department at Poznan Supercomputing and Networking Center since 2002. He received his M.Sc. degree in computer science, intelligent decision support systems, from the Poznan University of Technology, Poland in 2001 and Ph.D. in computer science from the same institution in 2009. Since 2008 he has been a deputy head of the department and now leads an energy-efficiency technologies group. His research interests include mainly energy efficient technologies, distributed systems, resource management & scheduling, and simulations.
Michal Kierzynka is employed at PSNC, where he focuses on parallel computing and new computing architectures and a Ph.D. student at Poznan University of Technology, Poland. He received his MSc in computer science from the same University in 2010. Between 2008 and 2010 he was employed at the Laboratory of Algorithm Design and Programming Systems at the Institute of Computing Science, Poznan, where he worked on pairwise as well as multiple biological sequence alignment on GPU. His scientific interests include mainly biological sequence alignment and DNA assembly.
Wojciech Piatek received his M.Sc. degree in computer science from the Poznan University of Technology in 2010. Since 2008, he has been working in the Applications Department at Poznan Supercomputing and Networking Center as a system analyst and developer. He participated in different infrastructure and research projects, such as PLPGrid and CoolEmAll.
Giovanni Agosta holds the position of assistant professor at Politecnico di Milano, Italy. His research interests focus on the interaction between compiler and hardware architecture. He has published over 60 papers in international journals and conferences, receiving 2 best paper awards and 4 HiPEAC paper awards, and has participated to 10 EU-funded research projects.
Alessandro Barenghi is assistant professor at Politecnico di Milano. His research fields cover the areas of applied cryptography, network security and the formal languages. He published over 60 papers in peer-reviewed international journal and conference proceedings. He is currently involved in the ECSEL SafeCOP and H2020 M2DC research projects, and is the program chair of the CS2 HiPEAC international workshop.
Carlo Brandolese since 2003 is assistant professor at Politecnico di Milano. He has been working until 1997 at Italtel as CAD Engineer, being responsible of the FPGA design flows and methodologies. Since 1997 he has been involved in several EU funded projects (SEED, INFORMA, SLAPS, PEOPLE, POET, WASP, COMPLEX). He has published more than 60 papers to international conferences and journals, gaining one best paper award. He is also author of 3 books on embedded systems.
William Fornaciari is associate professor at Politecnico di Milano. He published six books and around 200 papers, collecting 5 best paper awards, one certification of appreciation from IEEE and holds 3 international patents on low power design. Since 1993 he is member of program committees and chair of international conferences in the field of computer architectures, EDA and system-level design. Since 1997 he has been involved in 14 EU-funded international projects.
Gerardo Pelosi is assistant professor at Politecnico di Milano. His research fields cover the area of information security and privacy, and the area of applied cryptography. He published over 70 papers in peer-reviewed international journal and conference proceedings. He is currently involved in the ECSEL SafeCOP and H2020 M2DC research projects, and is the program chair of the CS2 HiPEAC international workshop.
Dr. Mario Porrmann is academic director in the research group Cognitronics and Sensor Systems, Center of Excellence Cognitive Interaction Technology, Bielefeld University. He received a Ph.D. in Electrical Engineering from the University of Paderborn, Germany in 2001. Mario Porrmann‘s main scientific interests are in on-chip multiprocessor systems, dynamically reconfigurable hardware and resourcePefficient computer architecture. Mario Porrmann has published more than 160 peer-reviewed papers in scientific journals as well as for international conferences. He is co-founder of EvoPACE GmbH.
Jens Hagemeyer studied electrical engineering combined with computer science at the University of Paderborn. He received his diploma degree from the University of Paderborn, Germany in 2006. He is a research assistant and Ph.D. student at Bielefeld University, in the area of FPGA-centric research topics.
Rene’ Griessl studied electrical engineering at the University of Paderborn, Germany, and received his diploma degree in 2012. He is a research assistant and PhD student at Bielefeld University, in the area of resource-efficient cluster servers and FPGA systems.
Micha vor dem Berge has studied Information Engineering at the Ostfalia University of Applied Science in Wolfenbuettel, Germany. He leads most of the Christmann’s research and development projects and published several papers and a book chapter in the context of efficient IT.
Wolfgang Christmann has studied engineering at the University of Hanover and worked as a teacher on a technical school. In 2005 he founded a start up which has a focus on resource efficient IT. At Cebit 2009 he was a speaker at the Conference of the German Department of Environment, the Federal Environment Agency and Bitkom (Green IT Forum). He is a member of the consortium for the “Blauer Engel fuer gruene Rechenzentren” (Blue Angel for Green Data Centers), a label initiative from the German ministry for ecology.
Stefan Krupop studied computer science at the Ostfalia University of Applied Sciences in Wolfenbuettel, Germany. He designs and develops firmware and higher level software.
Dr. Jean-Marc Philippe is a research engineer at CEA LIST, in the field of embedded parallel architectures. He received his Ph.D. degree in computer engineering from the University of Rennes I, France, in 2005. He has joined the CEA LIST in 2005. His research interests include self-adaptation techniques based on observation, control and actuators for high-performance and low-power computations as well as neuro-inspired processing chains.
Dr.-Ing. Sven Rosinger received the B.Sc. and M.Sc. degrees in embedded systems and the Ph.D. degree in engineering from the Carl von Ossietzky Universitaet Oldenburg in 2005, 2006 and 2012. In 2006 he joined the OFFIS - Institute for Information Technology and has been involved in several national and European research projects as researcher and project manager. He is the manager of the “Smart Resource Integration” group within the OFFIS Energy department.
Chris Adeniyi-Jones is a principal engineer in ARM’s corporate Research and Development division. Chris’ areas of research include many-core architectures, reconfigurable computing and software power optimization. He is the ARM coordinator for the Mont-Blanc and Mont-Blanc 2 projects.
Luca Ceva received the M.S. degree in computer engineering in 2010 from Politecnico di Milano. He currently covers the role of Technical Project Leader for Research and Development and Innovation porjects.
Udo Janssen studied technical informatics at the University of Applied Science in Emden, Germany. Since 2001 he is with CEWE and is responsible for the online operation of the CEWE Online Photo Services.