Elsevier

Microelectronics Journal

Volume 52, June 2016, Pages 104-110
Microelectronics Journal

A curvature-compensated CMOS bandgap with negative feedback technique

https://doi.org/10.1016/j.mejo.2016.03.011Get rights and content

Abstract

This paper propose a novel high-order curvature-corrected CMOS bandgap reference (BGR) utilizing the negative feedback structure. The innovative negative feedback bandgap core not only compensates the exponential nonlinearity of VBE but also improves the power supply rejection ratio (PSRR) and line regulation. The proposed BGR is analyzed and implemented in 0.35-μm CMOS process. Experimental results of the BGR indicate that a minimum temperature coefficient (TC) of 13 ppm/°C @−40 °C to 180 °C, a PSRR of −64 dB @ 100 Hz, and the 5.2 uV/V line regulation (LNR) from 3 V to 3.6 V supply voltage at room temperature. The active area of the presented BGR is 133 μm×300 μm.

Graphical abstract

In this paper, we proposed a new circuit configuration to improve a BGR׳s TC as well as the PSRR. The circuit adopt a negative feedback in the first-order voltage reference core area for a curvature corrected compensation and high PSRR. Till now, no bandgap voltage reference based on this technique has proposed in any paper.

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Introduction

Precision voltage reference plays an important role in ADC, DAC and LDO circuits. The temperature coefficient and power supply rejection ratio are two key factors defining the performance of the reference, and a low TC and high PSRR reference are highly preferred.

With regards to the non-linearity of emitter-base voltage of bipolar junction transistor (BJT), the TC of the first-order bandgap reference is limited between 20 and 100 ppm/°C [1], [2]. In order to improve temperature performance, some compensation techniques have been developed through the addition of a second-order or high-order proportional to absolute temperature (PTAT) term to the output reference voltage, which is denoted as curvature-corrected bandgap references [3].

In theory, T ln(T) correction is the best way to compensate the nonlinearity of VBE [1]. However, it is quite difficult to realize such advanced mathematical function with high accuracy in circuits. Most of the curvature-corrected BGRs use a proximate way to compensate this nonlinear component. A piecewise nonlinear squared-PTAT current flowing through MOSFET is added to the first-order BGR to compensate the nonlinear VBE in high temperature [4]. In either case, we could use PTAT and CTAT currents to implement the second-order curvature-compensation [5]. Instead of second-order compensation technique, a class of exponential and logarithmic curvature compensation is used to decrease the temperature drift in whole temperature range and achieves 5 ppm/°C [1]. High-order curvature-compensation also can be achieved by utilizing a variable gain current mirror to realize exponential compensation [6]. In BiCMOS, a diode connected bipolar transistor is used to generate a current proportional to the nonlinear T ln(T) and subtracted it from the current in core circuit [11].

In order to improve PSRR, a self-biased symmetrically matched current–voltage mirror is presented to enhance the PSRR up to −50 dB with 0.35 μm CMOS process [7]. Two negative feedback loops to achieve −80 dB PSRR performance with TSMC 0.35 μm CMOS process, which are the pre-regulator of line voltage and a negative feedback loop in the bandgap core [8]. The high PSRR strategies also include bandgap circuit operates from an internal regulated supply VREG made with a high gain feedback loop [9] or bandgap core is supplied from a current source independent from supply [10].

In this paper, we proposed new circuit architecture to improve a BGR׳s TC as well as the PSRR. The proposed circuit incorporates a negative feedback in the first-order voltage reference core architecture for the curvature corrected compensation and high PSRR. The proposed curvature compensation principle only requires an additional MOSFET. Curvature compensation is achieved by subtracting the non-linear current from Q2 BJT, while the solution presented in [11] use the dioded-connect BJT and subtracting the current from both Q1 and Q2. Till now, no bandgap voltage reference based on this proposed negative feedback technique has been proposed in any paper.

This paper starts with a brief analysis on the principle of classic bandgap references in Section 2. The proposed high-order curvature-corrected CMOS bandgap with negative feedback technique is introduced in Section 3. Simulated and measurement results, performance comparison with some other reported bandgap references are presented in Section 4. Finally, the conclusion is given in Section 5.

Section snippets

Principle of the first-order BGR

In CMOS technology, parasitic BJTs formed in n-well or p-well are commonly used to implement the bandgap voltage reference. Fig. 1 shows the traditional first-order CMOS BGR circuit [6]. The feedback loop constructed by P1P2 and N1N2 forces the voltage VA=VB, the current of R1 isI=VEB2VEB1R1=VTln(M(N+1))R1

where VBE means the emitter-base voltage of bipolar junction transistor, VT represents the thermal voltage and M is the emitter area ratio of Q1 and Q2. N means that P3 mirrors N times

Proposed curvature-corrected CMOS BGR with negative feedback

In addition to the quadratic, exponential, and piecewise compensation schemes, we propose an innovative negative feedback based compensation by adding a correction current to the PTAT collector current. The proposed bandgap reference circuit is shown in Fig. 2, and the deviations from the traditional design are highlighted. The BGR consists of voltage regulation, reference voltage generation, PSRR enhancement and start-up block.

Experimental results

The proposed BGR shown in Fig. 2 was implemented in TSMC 0.35 μm CMOS process As seen in Eq. (8), K is an important factor for curvature compensation and could be adjusted by the W/L of N3. Given W as 500 nm, we obtain the TC–L and the PSRR–L curves under different process corner in Fig. 3. Taking into account of the process variation, L=10 μm is a comprehensive selection. In TT process corner, the TC is as low as 8.34 ppm/°C and PSR is as high as 102 dB.

The operation of low temperature compensation

Conclusion

An innovative low TC and high PSR bandgap reference has been proposed and implemented by 0.35 μm/3.3 V CMOS technology in this paper. High-order temperature compensation and PSR enhancement are both achieved by a negative feedback in bandgap core circuit. A thorough analysis of the proposed curvature-corrected BGR architecture, along with the simulation and experimental results is presented. The proposed topology achieves a measured performance of a minimum 13 ppm/°C temperature coefficient with

Acknowledgments

The study is supported by Fujian PDST. Project no. 2010H6026 and China NSFC No. 61274133.

References (14)

  • Ze-Kun Zhou et al.

    A 1.6 V 25 μA 5 ppm/°C curvature-compensated bandgap reference

    IEEE J. Mag.

    (2012)
  • P.E. Allen et al.

    CMOS Analog Circuit design

    (2003)
  • Rincon-Mora

    Voltage References From Diodes to Precision High-Order Bandgap Circuits

    (2002)
  • Ruhaifi Abdullah Zawawi et al.

    An improvement of a piecewise curvature-corrected CMOS bandgap reference

    IEICE Electron. Express

    (2011)
  • Chuan Zhang, Shuzhuan He, Ying Zhu, et al., A high precision CMOS bandgap reference with second-order...
  • Xin Ming et al.

    A 1.3 ppm BiCMOS bandgap voltage reference using piecewise-exponential compensation

    Analog. Integr. Circ. Signal Process.

    (2011)
  • Yat-Hei Lam et al.

    CMOS bandgap references with self-biased symmetrically matched current–voltage mirror and extension of sub-1-V design

    IEEE J. Mag.

    (2010)
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