A VCO-based phase-expanding conversion designed for time-domain data converters
Introduction
A phase-expanding converter (PEC) is like an time-to-digital converter (TDC). The PEC quantizes specific time intervals with respect to a reference period of a clock while the TDC quantizes non-specific time intervals instead. In comparison with an analog converter, the PEC is truly all digital component, which has the advantages of programmability and easy calibration. In recent years, the supply voltage of a chip is getting lower than ever, since the gate length becomes shorter with the future advanced process. Quantization of analog signals such as current or voltage is more difficult than ever, thus the time-domain phase-expanding structures catch our attention.
Since the time-domain data converters, such as VCO based (counting) ADC [1], [2], [3], usually have a time residue that ‘could not be quantized to gain the resolution. In other words, those time-domain ADCs always have time residue less than one clock interval which represents the least significant bit (1 LSB). If we can convert the time residue into extra resolution in binary code and combine it with a data converter, we can then expand the resolution of the ADC. Therefore, through adopting this PEC is one of the solutions.
The PEC samples the time period between two signals usually named ‘Start’ and ‘Stop’, and calculates how many delay cells the ‘Start’ signal has passed through, thus encodes the quantity of the cells from thermometer code to binary code. Finally, we combine the resolution of the PEC within the time-domain data converters to gain additional resolutions, thus we can realize a higher resolution time-domain data converter.
The high-resolution data converters are generally the sophisticated analog design, hence the combination of the PEC and the time-domain data converter must be precisely matched. A traditional TDC is usually created with a delay chain of buffers [4], [5], [6], [7], [8], [9]. Two delay lines are implementations, such as those based on the Vernier delay cell [4], [5]. The silicon area is increased with the resolution. A time-to-voltage converter and a 5-bit flash ADC is designed to function as a TDC [6]. In [7], its TDC consist of coarse and fine time resolution. The more power consumption and large design area as the same as in [6], [7]. The Hierarchical delay is provided for fine resolution TDC [8]. The proposed structure is complicated and there is more power consumption. The time amplifier (TA) is designed for enhancing the resolution of TDC [9]. The TA is sensitive to the process-voltage-temperature (PVT) variations. In general, most of them are implemented with a chain of buffers, and triggers the flip-flop of each delay cell. However, this structure may not endure variations such as temperature and process, so that the control voltage (Vc) of the delay cell must be precisely controlled. In other words, a buffer-chain type TDC needs a calibration circuit to make sure that each of the delay cells has the same delay time.
This paper proposes a PEC, shown in Fig. 1, which can resist variations of process and temperature without any calibration circuit. Since the multiphase VCO generates both the phases and the clocks for the system, the phases are synchronous with the clocks, and the time periods between ‘Start’ and ‘Stop’ are synchronous with the clocks too. It means that if we use the same VCO to generate clocks of the desired system and the phases of the PEC, there is no need for the sensitive control voltage of the VCO or the calibration circuit of the phases.
This paper is organized as following: In Section 2 of this paper, the concept of the new delay chain architecture is presented to show how the resolution expands. In Section 3, the implementation of the PEC, which includes the multiphase VCO and the encoder designed for the multi-layer delay chain, will be presented. The HSPICE simulations and measurement results are reported in Section 4. Section 5 concludes this paper.
Section snippets
Concepts of proposed PEC
Here we want to introduce a PEC shown in Fig. 1. The system in the dotted line here is assigned to be a time-domain ADC [9]. The time residue less than 1 LSB of the ADC can be correctly converted into 6-bit binary codes, which adds the resolution of the whole system. Here we want to introduce a PEC, shown in Fig. 1, which is combined with a multiphase VCO and a time-domain ADC for example. We use the built-in multiphase VCO to generate clocks and phases for our multi-layer delay chain. Since the
Circuits description
This section introduces the remaining circuit of PEC. It consist of the multiphase delay chain, the multiphase VCO, and the encoder. As we have introduced the multi-layer delay chain circuits in Section 2, we will explain how the phases become the digital codes through the VCO and the encoder.
Fig. 4 shows the circuit of the multiphase VCO and Fig. 5 shows its cell. The VCO generates the Φ[1:16] for the delay chain, and these phases fed through the multi-layer delay chain. Fig. 6 shows the
Simulation and measurement results
The PEC architecture is post-layout simulated in 0.18 μm CMOS process. The ‘Start’ and ‘Stop’ signals may come from any time-domain data converters, such as the integrating ADC, or other circuits that need to convert a time residue into binary codes. We design a 6-bit fine resolution PEC with a 1 GHz multiphase VCO here.
In this section, we will use several methods to verify the function of the PEC, such as DNL/INL, jitter, and a sample with combination to a time-domain ADC. Fig. 10 is our testing
Conclusions
This paper presents a phase-expanding converter for time-domain analog-to-digital converters. Since the architecture is flexible due to designers, here we design a 6-bit multiphase PEC with a 4-layer delay chain. We use the 0.18 μm CMOS process to verify the function of our design, and implement with the time-domain ADC to further verify it. Simulation results show DNL ±0.21 LSB, and INL ±0.29 LSB. Experiment results show that the DNL is 0.52 LSB–0.13 LSB and the INL is 0.21 LSB–0.66 LSB.
Acknowledgment
This work is supported by National Science Council (NSC98-2221-E-182-049) and National Chip Implementation Center (NCIC). The author would like to thank I.-H. Wang and D.-L. Shen for their invaluable discussion.
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