A simple figure of merit to identify the first layer to degrade and fail in dual layer SiO x /HfO 2 gate dielectric stacks

Understanding the degradation dynamics and the breakdown sequence of a bilayer high-k (HK) gate dielectric stack is crucial for the improvement of device reliability. We present a new Figure of Merit (FoM), the IL/HK Degradation Index, that depends on fundamental materials properties (the dielectric breakdown strength and the dielectric constant) and can be used to easily and quickly identify the first layer to degrade and fail in a bilayer SiO 2 /HK dielectric stack. Its dependence on IL and HK material parameters is investigated and its validity is demonstrated by means of accurate physics-based simulations of the degradation process. The proposed FoM can be easily used to understand the degradation dynamics of the gate dielectric stack, providing critical insights for device reliability improvement.


Introduction
The adoption of the high-k/metal gate (HK/MG) technology beyond the 45 nm technology node [1] led to the replacement of the thin SiO 2 / SiON gate oxide of the MOSFET transistor with a bilayer dielectric stack, consisting of a relatively thin SiO 2 Interfacial Layer (IL) and a thicker overlying HfO 2 high-k (HK) layer. Besides ensuring further device scaling along the path indicated by the Moore's law [2], such change also revealed new behaviors and phenomena concerning overall transistor reliability (and especially gate oxide degradation dynamics), which have been ascribed mainly to the intrinsically higher defectivity of the HK and to its interaction with the underlying IL. One of the key aspects still most debated today concerns dielectric stack degradation and more specifically the identification of the first layer to degrade and fail: is it the SiO 2 -based IL or the overlying HfO 2 high-k? The studies published on this topic are about evenly split between the two possibilities: some indicate the HK layer as the primary source of dielectric stack degradation [3][4][5][6][7], while others identify the IL as the first layer to fail [8][9][10][11][12][13][14][15]. The presence of such controversial results supporting the two opposing theses can be ascribed to two main factors: i) the adoption of nonhomogeneous stress conditions, which may determine different degradation scenarios [16], and ii) the assumption that the SiO 2 -based IL possesses much better properties than the high-k layer (for example in terms of trap density and breakdown strength), which is not the case for the relatively thin SiO 2 layer inserted into the IL-HK bilayer stack. One thing remains obvious: a correct understanding of the degradation dynamics of the IL/HK dielectric stack (as well as of the underlying physics) is of critical importance for a proper interpretation of experiments and for the assessment and prediction of device lifetime.
The purpose of this work is twofold. First, we critically discuss and refute two key misunderstandings (or false myths) that are commonly reported in the literature to support and promote the idea that the high-k is the first material of the gate dielectric stack to degrade under electrical stress. Second, we propose a new figure of merit (FoM), that provides a quick and simple way to identify which layer is expected to degrade (and fail) first in a given IL/HK dielectric stack. The proposed figure of merit is analyzed as a function of specific material properties that are relevant for trap generation (that are, bond energy, dielectric constant and bond polarizability) and demonstrated by means of device simulations.

On the properties of the SiO 2 -based interfacial layer of a highk dielectric stack
Two common misunderstanding are usually made (by both academia and industry) when studying and analyzing the degradation and breakdown of high-k gate dielectric stacks comprised of a thin SiO 2 and a thicker overlying high-k (typically HfO 2 ).
First, there is the strong tendency of assuming the high-k material to be (by far) more defective than the SiO 2 -based IL, which is instead considered to be very similar to the high quality thermally grown silicon dioxide that was used as the gate dielectric of transistors until the advent of the HK/MG technology. Although this reasoning is substantially correct when considering single layers of the two materials, it does not apply when they are stacked together, due to the structural modifications caused to the IL by its interactions with the overlaying HfO 2 film. Several studies demonstrated that the SiO 2 layer of the high-k stack is typically sub stoichiometric [17] and as such characterized by a higher dielectric constant [18,19] and by a significant density of oxygen vacancy traps. The latter has been estimated to be in the range of 10 18 -5⋅10 19 cm − 3 [9,20,21] and thus comparable with the typical density of HfO 2 traps, 10 18 -10 20 cm − 3 [22,23]. In presence of a relatively thin HK layer (≤ 3 nm) these IL oxygen vacancies dominate the charge transport through the dielectric stack [24]. This is shown in Fig. 1 [24]. On the contrary, in the SiO x /HfO 2 gate dielectric stack the gate leakage current is dominated by the TAT component, while DT contribution is orders of magnitude smaller, see Fig. 1(b). Furthermore, simulations show that the charge transport is primarily assisted by the traps located in the IL [9,24]. Table 1 reports material and trap parameters used in the simulations.
The second common misunderstanding in the analysis of degradation and breakdown of the IL/HK gate dielectric stacks is related to the breakdown (or dielectric) strength (F BD ), an intrinsic property corresponding to the electric field at which an insulating material experiences breakdown. It has been experimentally demonstrated and is widely accepted that F BD is inversely proportional to the material dielectric constant [28,29]. Consistently, SiO 2 is characterized by a much higher F BD (in the 10-20 MV/cm range) with respect to Hafnium oxide (in the 4-7 MV/cm range) [30,31]. This leads to the general belief that HfO 2 is the first layer to degrade in the high-k gate dielectric stack, since its breakdown strength is by several times smaller than the one of the Silicon dioxide-based interfacial layer. Again, this reasoning applies only when the two materials are considered separately, but not when they are stacked together as in the case of the high-k dielectric stack. In the latter case, there is another important factor that must be taken into consideration: the applied electric field redistributes according to Gauss's law and will be higher in the material with the lowest dielectric constant (κ). Therefore, any consideration on the degradation of the materials composing the stack cannot be made only by considering the breakdown strength, but must also take into account the difference between their dielectric constants, which determines the internal field redistribution. It will be the balance between the ratios of F BD and κ of the different materials that will ultimately determine what layer of the stack will degrade and break first.
The two common misunderstandings just discussed may wrongly promote and strengthen the idea that the HK is the first layer to degrade and fail in a bilayer IL/HK stack. In the next section we will derive and define a new Figure of Merit that unambiguously provides a clear indication about the first layer that is expected to break in a bilayer stack.

A new figure of merit: the IL/HK degradation index
As discussed in the previous Section, any analysis or consideration about the breakdown of the materials composing a multi-layer dielectric stack must take into account both the breakdown strength and the dielectric constant of the different layers. The first defines the value of the electric field at which the specific material is subject to breakdown. The latter determines the field redistribution within the different layers of the stack and thus the electric field to which each layer is subjected. Here we define a FoM incorporating these two key properties (F BD and κ) into a simple formula allowing determining which layer of an IL/HK bilayer dielectric stack is expected to experience breakdown (and degradation) first.
First of all, the breakdown process of a given dielectric layer subjected to electrical stress is determined by the electric field it experiences. Adopting the effective energy formalism [30,32,33], the rate G (or trap generation rate) in the dielectric can be expressed as a function of temperature (T) and field (F) as: G 0 is the bond vibration frequency, E A the zero-field bond-breakage activation energy, b = p 0 (2 + κ)/3 the bond polarization factor (p 0 is the active dipole moment and κ the relative dielectric constant), and k B the  Table 1. Boltzmann's constant. F BD = E A /b is the so-called breakdown strength [29,30], that in (1) identifies the field corresponding to the maximum bond breaking rate (G = G 0 ). From (1), it is clear that the magnitude of the external field F with respect to the breakdown field F BD provides information on the dielectric degradation rate (note that this is valid independently on the considered breakdown model). Therefore, we can define a degradation metric for a given material as the ratio between the electric field F at which is subjected and its breakdown strength F BD . For the IL and HK layers of a highk dielectric stack we have: where F IL , F HK and F BD,IL , F BD,HK are respectively the electric field and the breakdown strength of IL and HK layers. As the electric field across the layer approaches F BD , the degradation rate in the dielectric increases until it reaches breakdown conditions when F = F BD [for which G is maximum, see (1)] that is, when D = 1.
From (2) and (3) follows: By applying the Gauss' law to the two layers one can relate F IL and F HK in (4) to each other and to their dielectric constants [10]: where κ IL and κ HK are the relative dielectric constants of IL and HK layers, respectively. Eq. (5) can be used to determine the ratio between the electric fields in the HK and IL, which is equal to the inverse ratio of the relative dielectric constant: F HK /F IL = κ IL /κ HK . When this is substituted into (4) we obtain That we define as the IL/HK Degradation Index DI IL/HK , a simple, field-independent figure of merit indicating which among HK and IL is expected to degrade and break first. It must be noted that the ratio between the breakdown strengths, F BD,IL /F BD,HK , is always higher than one (as discussed in Section 2), whereas the ratio between the dielectric constants (that represents the ratio between the electric fields), κ IL /κ HK , is always smaller than one. It is therefore the balance between these two quantities, expressed by the IL/HK Degradation Index, that determines which layer breaks first. When DI IL/HK < 1, this balance favors the degradation of the IL, that thus breaks faster than the HK. When DI IL/HK > 1, the opposite applies. BD conditions are reached earlier in the HK, that will thus degrade and break faster than the IL.
Using (6) to calculate the IL/HK Degradation Index considering typical material parameter for SiO 2 IL and HfO 2 HK layers ( Table 2) indicates that degradation is more likely to occur first in the interfacial layer, since DI IL/HK is always smaller than one (from 0.35 to 0.84). It must be noted that the dielectric constant of the IL can be significantly higher than the one of the pure SiO 2 , due to its sub-stoichiometric nature [18,19] which is not accounted for in most of the cases reported in Table 2. The exact κ IL value depends on the process conditions and on the thicknesses of the IL and HK layers. Relative IL dielectric constants of 5-6 [14,24], 7.5 [19] and 9 [19] have been reported for IL thicknesses around 10 Å, 5 Å and 3 Å, respectively (with HfO 2 thicknesses in the 20-40 Å range). Similarly, theoretical calculations show that the κ IL is expected to increase to values of ~6 and ~ 10 for thicknesses of 5 Å and 3 Å, respectively [18]. However, even taking into account a higher κ IL = 6 for all the cases in Table 2 (a quite reasonable value for an IL in the 8-10 Å thickness range), the IL/HK Degradation Index remains smaller than one, indicating that the degradation of the high-k stack is still expected to be controlled by the Interfacial Layer (not shown).
Based on these results and considerations, an early degradation and breakdown of the HK layer seems unlikely and possible only in presence of a highly sub-stoichiometric IL (characterized by a κ IL higher than the 3.9 of stoichiometric SiO 2 ) and/or a value of the HK relative dielectric constant lower than 20 (that is typically too small for its use in a high-k gate dielectric stack). The impact of IL and HK material parameters on the IL/HK Degradation Index will be addressed in the next Section.

Simulation results and discussion
Simulations are performed with Applied Materials' commercial semiconductor device simulation software Ginestra® [25], which provides a comprehensive and self-consistent description of charge trapping and transport [34], degradation phenomena [26,35,36], and material modifications in the considered material stacks. The conduction through dielectric materials is described accounting simultaneously for a variety of charge transport mechanisms, such as direct/Fowler-Nordheim tunneling, drift-diffusion in conduction/valence and defect bands, thermionic emissions, and trap assisted tunneling (TAT), the latter implemented in the framework of the multi-phonon theory [24,[37][38][39]. An example of the related material and trap parameters is reported in Table 1 for the charge transport simulations in Fig. 1. Charge transport equations are self-consistently solved together with the Poisson's equation (accounting for defects charge state and occupation), the Fourier's equation (for the calculation of power dissipation and temperature increase within the material stack [35]) and the equations describing atomic-level material modifications originating from electrical/thermal stresses [26,35,36,40]. The atomistic processes responsible for the creation of new defects are implemented using the effective energy formalism [30,32,33], see eq. (1) in Section 3. The stochastic nature of the trap generation process is accounted for by exploiting the Monte Carlo technique described in [41]. In this work (1) is used in its simpler form, in which E A and b are macroscopic quantities providing an equivalent description of more complex microscopic processes (typically involving bond weakening induced by carriers' injection and trapping into pre-existing defects [26,35,36]). Such a macroscopic description of the bond-breakage process is more suitable for the scope of this work.
Finally, it is important to underline again that the breakdown field of a given material can be calculated as the ratio between E A and b in (1) [30]. This provides a direct connection between (1) and (6) that will be exploited in the following to analyze the dependence of the FoM introduced in Section 3 on specific IL and HK material properties and thus understand under which conditions the degradation of the IL/HK dielectric stack is expected to be dominated by one layer or the other. Figure 2 shows four contour plots of the IL/HK degradation index calculated as a function of IL and HK relative dielectric constants. They are obtained considering different values of IL and HK breakdown strengths, matching the experimental limits derived in [31] [ Fig. 2(a), (b)], and to the theoretical values reported in [30] [ Fig. 2(c), (d)]. The yellow stars on the plots identify five specific points matching to the κ IL and κ HK values of typical IL/HK dielectric stacks (1: κ IL /κ HK = 3.9/25; 2: κ IL /κ HK = 3.9/21; 3: κ IL /κ HK = 6/25; 4: κ IL /κ HK = 6/21; 5: κ IL /κ HK = 9/   Table 3) as the HK layer of the stack. Black solid lines indicate the level curve corresponding to DI IL/HK = 1. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.) 25). They are representative of stacks with thick (≥ 12 Å, points 1 and 2), thin (8-10 Å, points 3 and 4) and very thin (3 Å, point 5) IL and a HfO 2 thicknesses in the 20A-40 Å range (see also discussion in Section 3). As can be seen, these points are almost always located in the region characterized by DI IL/HK < 1 (that is, the blue region below the solid black line), suggesting that the earlier degradation of the interfacial layer can be expected in most of the cases. Only when the ratio between IL and HK breakdown strength is high (roughly speaking, larger than 3.5), as in Fig. 2(c), or the IL dielectric constant is high, as for point 5 in Figs. 2(a)-(c), DI IL/HK > 1 and the degradation is expected to start in the high-k layer. It is worth noting that also a smaller high-k dielectric constant (below 20) significantly increases the probability to have DI IL/ HK > 1 and thus the HK as the first layer to break (it would correspond to a left shift of the considered κ IL /κ HK point in Fig. 2). The IL/HK degradation index is reported in Fig. 3 as a function of high-k material properties, the relative dielectric constant and the breakdown strength, while considering F BD,IL = 15MV/cm and three different values of the IL relative dielectric constant (typical of different IL thicknesses, as already discussed). The symbols on the plots identify the DI IL/HK values calculated when considering the specific materials listed in Table 3 as the HK layer of the IL/HK stack: HfO 2 /HfO x (green pentagons), ZrO 2 (orange diamonds), Al 2 O 3 (yellow squares), and HfAlO (blue triangle). Note that in these cases the HK breakdown strength has been calculated as the ratio between the zero-field bond-breakage activation energy E A and the bond polarization factor b, whose values are either provided in the indicated references or extracted from the reported time-dependent dielectric breakdown experimental data using the methodology in [23]. As discussed above, these numbers are macroscopic quantities providing an equivalent description of the more complex microscopic degradation processes involving bond weakening induced by carriers' injection and trapping into pre-existing defects [26,35,36]. Fig. 3 shows that all the calculated data points are located in the region characterized by DI IL/HK < 1 (the blue region above the solid black line) when the relative dielectric constant of the underlying IL is either 3.9 or 6, see Figs. 3(a), (b). Therefore, degradation is expected to occur first in the IL when considering any of the materials in Table 3 as the HK layer of the stack. Only in the case of a higher κ IL (> 6), which corresponds to a thin IL (below ~8 Å), the breakdown of some of the considered stacks will be driven by the degradation of the HK layer, see Fig. 3(c).
Besides providing a clear indication about the first layer to degrade and fail in a bilayer IL/HK dielectric stack, the proposed FoM and the results in Figs. 2 and 3 allow understanding the role of material parameters on the degradation dynamics, which is critical for the improvement of device reliability. Once the weak layer is identified, the analysis performed here can be used to understand how the material properties of the stack can be improved to extend device lifetime and reliability margins. Noticeably, the proposed approach is general and can be also applied for understanding the forming/degradation dynamics of devices comprising a multilayer dielectric stack, such as memory capacitors [42], resistive random-access memories (RRAMs) [43], and memristors [44].
In order to prove the validity of the proposed FoM we used the Ginestra® [25] modeling framework to simulate the degradation dynamics of two SiO x /HfO 2 dielectric stacks, whose thicknesses, materials properties and IL/HK degradation indexes are reported in Table 4 [stack #1 and #2 respectively correspond to points 2 and 4 in Fig. 2(c)]. From the calculated degradation indexes, dielectric breakdown is expected to be driven by the degradation of the SiO x IL in stack #1 (DI IL/HK = 0.7), and of the HK in stack #2 (DI IL/HK = 1.07). Simulations are performed considering a constant voltage stress (CVS) with stress voltages (V STRESS ) of 3.1 V and 1.6 V, selected to induce the same equivalent electric field, F EOT = V STRESS /EOT. Simulations stop as soon as the gate current reaches 10 μA.
Simulations results shown in Figs. 4 and 5 respectively for the 12 Å/ 30 Å SiO x /HfO 2 and 8 Å/20 Å SiO x /HfO 2 devices provide a detailed understanding of the degradation process in the bilayer gate dielectric stack. They show the evolution of oxygen vacancies distribution (along the thickness and in the X, Y plane), the 2D temperature map in the X, Y plane, and the current driven by traps in the X, Y plane. As expected, the two devices considered exhibit rather different degradation dynamics.
In the case of stack #1, oxygen vacancy traps are first generated only into the IL, Fig. 4(b), consistently with the calculated DI IL/HK of 0.7. The device is in the so-called Stress-Induced Leakage Current (SILC) stage, characterized by uniform degradation, Fig. 4(b), temperature profile, Fig. 4(f), and current distribution, Fig. 4(j). Traps continue to be generated uniformly in the IL volume until the formation of a BD spot with a larger local concentration of oxygen vacancies (up to 10 21 cm − 3 ), Fig. 4(c), bringing the device into the soft/progressive BD stage (SBD/ PBD) stage. Besides causing a small increase of local temperature, Fig. 4 (g), and current, Fig. 4(k), this event determines a significant redistribution of the internal electric field, since now the applied stress voltage falls almost entirely on the unbroken HfO 2 layer. This triggers a massive defect generation in the HK, Fig. 4(d), eventually leading to the BD of the entire dielectric stack (hard BD phase). Note that the defect generation in the HK is localized almost entirely in correspondence of the initial IL BD spot and is accompanied by a significant increase in the local temperature, Fig. 4(h), and current, driven mainly by the BD filament, Fig. 4 (l).

Table 3
Relative dielectric constant (κ HK ), zero-field bond breakage activation energy (E A ), active dipole moment (p 0 ) and bond polarization factor (b) reported in the literature for different HK material, and the corresponding calculated breakdown strength ( = E A /b) and IL/HK degradation index (for F BD,IL = 15MV/cm and three different κ IL values as in Fig. 3  The results of the simulated CVS on stack #2 are shown in Fig. 5. Differently from the case of stack #1 and in agreement with the value of the defined FoM (DI IL/HK = 1.07), in this case the degradation starts in the HK layer, Fig. 5(b). Once traps start to be generated, the evolution of the degradation is similar to what discussed already for stack #1, although the role of the IL and HK layers is inverted. Stress-induced oxygen vacancies are generated uniformly within the entire HfO 2 volume, Fig. 5(b), until the formation of one or more SBD spots, Fig. 5(c), that typically drive more current than the rest of the device, Fig. 5(k).
Eventually, the current flowing through one of these SBD spots reaches a value high enough to determine an increase in the local power dissipation and temperature, Fig. 5(g). This, in turn, increases the local trap generation rate, thus forcing subsequent oxygen vacancies to be created preferentially nearby the hot spot. This triggers a thermally driven positive feedback that quickly leads to the breakdown of the entire stack, with the propagation of the HK BD spot into the underlying region of the IL, Fig. 5(d).
It is worth to underline that the simulation results shown in Figs. 4 and 5 are just a single statistical example. Although the general behavior will be the same for all nominally equivalent devices, some variations are expected in the final configurations of the generated traps, for example in terms of size, shape and number of initial SBD spots as well as in terms of size and shape of the final HBD spot. Nevertheless, the results shown in Figs. 4 and 5 confirm the validity of the proposed FoM, the IL/ HK degradation index, as a simple end efficient way to understand what layer of a bilayer gate dielectric stack is expected to degrade and break first.

Conclusions
We presented a new Figure of Merit, the IL/HK degradation index, that allows to understand what layer of a bilayer gate dielectric stack is expected to degrade and break first when subjected to electrical stress. The dependence of the FoM on IL and HK material parameters has been investigated and its validity has been demonstrated by means of accurate physics-based simulations of the degradation process. The proposed IL/HK degradation index can be easily used to understand the role of material parameters on the degradation dynamics of the gate dielectric stack, providing critical insights for device reliability improvement.

Declaration of Competing Interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Data availability
Data will be made available on request.