Elsevier

Microelectronic Engineering

Volume 103, March 2013, Pages 144-149
Microelectronic Engineering

A comprehensive study of channel hot-carrier degradation in short channel MOSFETs with high-k dielectrics

https://doi.org/10.1016/j.mee.2012.10.011Get rights and content

Abstract

This paper presents a comprehensive study on channel hot-carrier (CHC) degradation in short channel MOSFETs with high-k dielectric. Different reliability scenarios are analyzed, i.e., temperature influence, impact of high ID and dynamic operation conditions. To explain the CHC damage behavior in short channel devices, we divide the total CHC degradation in two components: the classical CHC damage located at drain side and the degradation produced by the voltage drop over the gate dielectric, which can be considered as bias temperature instability (BTI).

Graphical abstract

The channel hot-carrier aging is divided in two independent components: CHC at the drain side and BTI along the inversion channel. This split up explains the overall device performance in front of several reliability environments.

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Highlights

► We confirm that degradation during CHC stress is caused by two components. ► At high VG BTI dominates and the CHC degradation does not follow the LEM. ► For AC CHC stress, at VG = VD CHC condition a quasi-static behavior is observed.

Introduction

The performance of ultra scaled CMOS devices is affected by several degradation mechanisms, being one of the most important the channel hot-carrier (CHC) degradation [1], [2], [3]. Basically, the CHC wear-out is caused in the on-state of MOSFET transistors when they are subjected to gate voltages (VG) larger than the threshold (VT) and, simultaneously, to a drain voltage (VD) larger than the saturation drain voltage. This voltage configuration produces a maximum electric field located close to the drain region, which provokes the injection into the gate dielectric of high energetic electrons and holes (hot-carriers), created by impact ionization, at the pinch-off region. Consequently, the injected hot-carriers damage the insulating properties of the dielectric affecting the device performance [4]. While the electrons are mostly collected at the drain, holes are repelled from the gate/drain and flow towards the substrate [4]. The obtained substrate current (ISUB) is often used to monitor the hot-carrier generation [5], and the peak observed in the ISUB–VG curve, measured at a fixed VD, corresponds to the most damaging CHC condition [6].

Last decades, CHC stress has been deeply studied in devices with large dimensions [6], [7] and was considered to be less relevant for the device reliability analysis when the bias voltage and device dimensions were reduced in the same proportion [8]. Meanwhile, the bias temperature instability (BTI), which produces a change in the transistor VT when a VG is applied, increasing the effect at high temperature, was becoming more significant [9]. Nevertheless, for the recent nodes, CHC degradation has acquired a renewed relevance since supply voltage scaling is slowing down, due to the non-scalability of the sub-threshold slope, although the gate-length is continuing to scale down below 40 nm [1], [10]. Consequently, this leads to an increase of the lateral electric field and enhanced CHC degradation. Furthermore, with the reduction of the devices channel length a modification of the CHC wear-out behavior has been observed: whereas for long channel nMOS the most CHC damaging stress condition is produced when VG = VD/2, for short channel devices (L < 0.15 μm) a shift of the most damaging CHC stress condition to VG = VD is obtained [3], [11], [12]. Otherwise, for pMOSFETs, the most damaging CHC stress condition is always obtained at VG = VD, independently of the channel length, since this condition takes place when the highest hole injection into the oxide is produced [13], [14] for both long and short channel pMOS. Thus, for short channel devices VG = VD is the most damaging CHC condition, independently of MOSFET type (n or p) [14].

On the other hand, high-k materials have been introduced recently to reduce the gate leakage currents present in ultra-thin (lower than 1.5 nm) SiO2 based dielectrics [15]. Higher k values allow a physically thicker dielectric layer resulting in a significant reduction of the gate leakage current. However, the properties of these high-k materials are not as good as for SiO2 [16] mainly in terms of stability with the substrate and carriers mobility. Hf-based high-k materials are considered the best candidates to substitute SiO2 as gate oxide [16], and a complete reliability study of Hf-based MOSFETs is being developed in last years [2].

This work analyzes the CHC degradation in short channel MOSFETs based on high-k dielectrics. The paper is divided in the following sections where different scenarios are analyzed. Section 2 describes the devices and characterization methods used in this work. Section 2.1 shows the effect of temperature on CHC degradation. Section 2.2 assesses the nMOS performance under the present operating conditions, that is, high ID values. Finally, Section 2.3 analyses the CHC damage when AC stress conditions are applied.

Section snippets

Experimental

The samples used in this study were n- and p-MOSFETs with a Highly Doped Drain (HDD) structure. The dielectric stack was always based on SiO2/HfSiON, with a ∼0.7 nm thick chemical SiO2 interface, followed by a Metalorganic Chemical Vapor Deposited (MOCVD) 3 nm thick high-k layer. Samples with different Hf-percentage and gate electrodes were used, which will be described at the beginning of each section. The device nominal dimensions were 1 μm for the width and 0.13 μm (70 nm effective) for the

Conclusions

A detailed study of CHC degradation in short and long channel MOSFETs based on high-k dielectrics has been performed. The high temperature studies have confirmed that in short-channel transistors (L < 0.15 μm) subjected to CHC stress at VG = VD, the degradation unexpectedly increases with temperature. To explain this observation, we have considered that the CHC degradation is split up into two components [3]: (1) the damage produced by the oxide field applied between gate and source/inverted channel

Acknowledgments

This work has been partially supported by the European Union (APROTHIN Project), the Spanish MICINN (TEC2010-16126 and JCI-2010-07083) and the Generalitat de Catalunya (2009SGR-783).

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    KU Leuven, ESAT Department Leuven, Belgium.

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