Characterization and modeling of RF substrate coupling effects in 3D integrated circuit stacking
Introduction
With increasing interconnect densities and rising cost of integrated circuit (IC) manufacturing, 3D architectures for IC integration are a promising alternative to standard 2D designs. 3D technology is facing many technological challenges, like completion of vertical interconnects in silicon substrates (Through Silicon Vias, TSV) which ensure the signal transmission, bonding with alignment of functional dies and substrate thinning; on another hand we can notice a lot of benefits in circuit performances.
One of main advantages of 3D technologies, is that it enables the solving of the on-chip interconnect problem by partitioning a large chip into smaller ones, which can then be interconnected vertically using the shortest path. Electrical performance of each chip and global interconnect delays are improved. Another benefit of 3D integration is the possibility to stack different types of dedicated and high performance IC (memories, CPU, RF, optical sensor, …). So an increasing number of functionalities are now possible in the same IC. Nevertheless with these sophisticated 3D systems, parasitic coupling effects may occur in Si substrates. They are predominantly generated by HF signals propagated through TSV and especially observed between neighboring TSV and between and CMOS [1]. Substrate coupling effects have capacitive, inductive or conductive origins. Thus wide band electromagnetic modeling and high-frequency characterization are necessary to quantify and predict substrate coupling effects in 3D integrated circuits.
In this paper, we mainly analyze substrate coupling effects when HF signals are propagated along TSV. First, several dedicated test structures are studied using HF modeling and HF measurements. Three test structures are used:
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A capacitor directly integrated in the thinned Si substrate. Each electrode of this capacitor is realized using a dense wall of TSV, positioned in a parallel configuration. This test structure is named “TSV capacitor” and described in Fig. 1.
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A set of two TSV, electrically coupled through the Si substrate. Diameter and height of each TSV are, respectively, 3 and 15 μm; coupling distance between TSV is 11 μm. This test structure is named “coupled TSV” and described in Fig. 2.
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A set of two parallel and coupled transmission lines directly integrated in the thinned Si substrate. Each transmission line is designed and realized using a long TSV as signal line. Ground plane is located on the bottom face of the Si substrate. This test structure is named “TSV transmission lines” and described in Fig. 3.
HF modeling results are compared to HF measurement results to validate the electromagnetic modeling software as a predictive tool. Then, electrical equivalent models are extracted to simulate and quantify substrate coupling phenomena. Finally, parametric analyses are also performed to evaluate substrate coupling effects when dimensions and material properties of TSV and substrate vary.
Section snippets
Electromagnetic modeling
Electromagnetic (EM) modeling is performed using a full wave 3D solver simulator Ansoft HFSS from 40 MHz up to 40 GHz. This simulator works using Finite Element Method (FEM) based on Maxwell equations and adaptive meshing. In this simulation system where the basic meshing element is a tetrahedron, FEM permits the resolution of all kinds of 3D structure. The geometry of the model, treated in HFSS, is automatically divided into a big number of tetrahedrons. By dividing the structure into small
Results and discussions
In the continuity of previous predictive studies [3], where the “TSV capacitor” structure (Fig. 1) has been studied, we have demonstrated that each wall of TSV is equivalent to a planar electrode and the set of two walls of TSV equivalent to a planar capacitor. So, electrical fields are generated in the Si substrate by TSV. In conclusion, capacitive coupling effects are created by TSV through the Si substrate and proportional to the density of TSV, as shown in Fig. 4 where the capacitance of
RF measurements
In order to confirm our simulations, a new structure has been designed for RF measurements. The test structure (Fig. 3) is an extension of the cross-section of the two coupled TSV structure (Fig. 2) within the silicon substrate to compose two coupled lines. The two coupled lines have a width of 3 μm and are separated by a distance of 11 μm just like the two coupled TSV structure (Fig. 2). For measurements, we used an ANRITSU 37397C two ports Vector Network Analyzer (VNA). Measurements have been
Conclusion and perspectives
In conclusion, results shown in this paper point out the impacts and effects of silicon substrate in terms of capacitive, conductive and inductive coupling over a large band of frequencies (40 MHz up to 40 GHz). Thus, as shown in previous paragraphs, modifying parameters such as dimensions or material properties has large effect on the coupling and can give solutions to reduce it significantly.
In parallel to HF electromagnetic simulations, measurements are done on a dedicated test structure and
Acknowledgment
The authors would like to acknowledge the cluster “Micro Nano” of the French Rhône-Alpes Region, under the “ICE3” project, for supporting these researches.
References (5)
- M. Rousseau, M.-A. Jaud, P. Leduc, A. Farcy, A. Marty, Impact of substrate coupling induced by 3D-IC architecture on...
- HFSS Three-dimensional Electromagnetic Simulation Program, Ansoft Corporation, Pittsburgh, PA,...
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