Low-power-consumption CMOS inverter array based on CVD-grown p-MoTe2 and n-MoS2

Summary Two-dimensional (2D) semi-conductive transition metal dichalcogenides (TMDCs) have shown advantages for logic application. Complementary metal-oxide-semiconductor (CMOS) inverter is an important component in integrated circuits in view of low power consumption. So far, the performance of the reported TMDCs-based CMOS inverters is not satisfactory. Besides, most of the inverters were made of mechanically exfoliated materials, which hinders their reproducible production and large-scale integration in practical application. In this study, we demonstrate a practical approach to fabricate CMOS inverter arrays using large-area p-MoTe2 and n-MoS2, which are grown via chemical vapor deposition method. The current characteristics of the channel materials are balanced by atomic layer depositing Al2O3. Complete logic swing and clear dynamic switching behavior are observed in the inverters. Especially, ultra-low power consumption of ∼0.37 nW is achieved. Our work paves the way for the application of 2D TMDCs materials in large-scale low-power-consumption logic circuits.

A practical approach to fabricate large-scale CMOS inverter arrays is demonstrated A method to balance the current characteristics of the channel materials is developed Complete logic swing and clear dynamic switching behavior are observed Ultra-low power consumption of 0.37 nW is achieved

INTRODUCTION
Over the years, two-dimensional (2D) materials such as graphene and transition metal dichalcogenides (TMDCs) have stimulated great research enthusiasm, owing to their unique electronic and optoelectronic properties and ultrathin geometry (Akinwande et al., 2019;Fiori et al., 2014;Liu et al., 2021). Graphene, with high conductivity and high carrier mobility, has been extensively studied (Castro Neto et al., 2009;Flory et al., 2020;Novoselov et al., 2005;Yu et al., 2013). However, because of its gapless nature, graphene is not a good channel material for field-effect transistor (FET), which requires efficient electrostatic control. Semi-conductive TMDCs, with larger bandgaps, surpass graphene in this aspect. Recently, n-channel metal-oxide-semiconductor inverters  and p-channel metal-oxide-semiconductor inverters (Zhang et al., 2019) based on TMDCs have been reported. Complementary metal-oxide-semiconductor (CMOS) inverter, composed of an n-channel and a p-channel FET, has advantage in reducing power consumption and therefore is an important component in integrated circuits. However, so far, the performance of the reported TMDCs-based CMOS inverters is not satisfactory. They suffered from high power consumption Pu et al., 2016) or large leakage current . Besides, most of the CMOS inverters were made of mechanically exfoliated TMDCs (Cho et al., 2019;Jeon et al., 2015;Pezeshki et al., 2016), which hinders their reproducible production and large-scale integration in practical application. Recently, large-area growth in a cost-effective way has been realized for several TMDCs via chemical vapor deposition (CVD) method (Pu et al., 2016;Wang et al., 2019;Xu et al., 2019a). The as-grown MoTe 2 (Xu et al., 2019b) and MoS 2  are pand n-type, respectively. Moreover, it is demonstrated that atomic layer deposition (ALD) of Al 2 O 3 under certain conditions can cause n-type doping to 2D materials, including graphene (Zheng et al., 2015), MoS 2 (Li et al., 2017), and MoTe 2 (Lim et al., 2017;Park et al., 2019).
In this study, we fabricate CMOS inverter arrays using large-area CVD-grown p-MoTe 2 and n-MoS 2 . We have developed a method to balance the current characteristics of the channel materials. Complete logic swing is obtained in our inverters. High voltage gain ($23, much larger than 1) and noise margins close to ideal values are obtained. Especially, ultra-low peak power consumption of $0.37 nW is achieved, which is among the lowest power consumption values reported so far for TMDCs-based CMOS inverters under similar measurement conditions (Cho et al., 2019;Jeon et al., 2015;Pezeshki et al., 2016). We also investigate the dynamic switching behavior of the CMOS inverters and observe satisfying rising time t r (several

RESULTS AND DISCUSSIONS
Figures 1AÀ1E are the corresponding optical images after each fabrication step, illustrating the fabrication process of our CMOS inverter array and demonstrating the feasibility of the large-scale fabrication method. First, arrayed Ti/Au (10/50 nm) electrodes were fabricated on a SiO 2 (285 nm)/p + -Si substrate as buried gates for both of MoTe 2 and MoS 2 FETs. Then a 20-nm-thick Al 2 O 3 dielectric layer was deposited on the (C) Pairs of Pd/Au (10/50 nm) source and drain electrodes (Electrodes 1 and 2 in (F)) were fabricated on the ends of each MoTe 2 sheet. After that, a 3-nm-thick Al 2 O 3 layer was deposited on the whole substrate to protect MoTe 2 from subsequent steps. (D) Pairs of Pd/Au (10/50 nm) source and drain electrodes (Electrodes 3 and 4 in (F)) were fabricated on the Al 2 O 3 layer. Herein, Electrode 3 and Electrode 2 have an overlapping area in the vertical direction (outlined by the black dashed lines) for measurement purpose. (E) The MoS 2 channels (outlined by the blue dashed lines) were fabricated by transferring and patterning a CVD-grown MoS 2 film. Finally, a 5-nm-thick Al 2 O 3 layer was deposited on the whole substrate, which caused an n-type doping effect on MoS 2 . (F) The optical image of a single inverter in the CMOS inverter array. The red, blue, and black dashed lines outline the MoTe 2 sheet, the MoS 2 sheet, and the overlapping area of Electrodes 2 and 3, respectively. To construct a complete CMOS circuit, the buried Gate Electrode and Electrode 1 were connected to V in and V dd , respectively. Electrodes 2 and 3 were connected to a digital oscilloscope by a tungsten needle for V out extraction. Electrode 4 was grounded. iScience Article substrate via ALD method ( Figure 1A). Second, a CVD-grown MoTe 2 film (see Method details) was transferred onto the Al 2 O 3 layer from the growth substrate with the help of polymethyl methacrylate (PMMA) and deionized water, which avoids the common use of hydrofluoric acid (Pu et al., 2016;Xu et al., 2019b). The transferred MoTe 2 film was patterned (see Method details) into rectangular sheets (outlined by the red dashed lines) over the buried gates ( Figure 1B). Third, pairs of Pd/Au (10/50 nm) source and drain electrodes (Electrodes 1 and 2) were fabricated on the ends of each MoTe 2 sheet. After that, a 3-nm-thick Al 2 O 3 layer was deposited on the MoTe 2 FET array to protect MoTe 2 from subsequent steps ( Figure 1C). For fabricating the MoS 2 FET array, pairs of Pd/Au (10/50 nm) source and drain electrodes (Electrodes 3 and 4) were fabricated on the Al 2 O 3 layer ( Figure 1D). Herein, Electrode 3 and Electrode 2 have an overlapping area in the vertical direction (outlined by the black dashed lines) for measurement purpose. Similarly, MoS 2 channels (outlined by the blue dashed lines) were fabricated by transferring and patterning a CVD-grown MoS 2 film (see Method details). Finally, a 5-nm-thick Al 2 O 3 layer was deposited on the whole substrate ( Figure 1E), which caused an n-type doping effect on MoS 2 . Figure 1F is the optical image of a single inverter in the CMOS inverter array. To construct a complete CMOS circuit, the buried Gate Electrode and Electrode 1 were connected to the input voltage (V in ) and supply voltage (V dd ), respectively. Electrodes 2 and 3 were connected to a digital oscilloscope by a tungsten needle for output voltage (V out ) extraction. Electrode 4 was grounded. The cross-sectional schematic of the device structure depicted in Figure 1F is shown in Figure 1G. The CMOS circuit diagram is shown in the inset of Figure 3C. Notably, in this work, we fixed the MoS 2 FETs' channel length (15 mm) and changed the MoTe 2 FETs' channel lengths to make their current characteristics balanced. The optical image of the CMOS inverter array is presented in Figure S1C.
The MoTe 2 films ( Figure S1A) used in our devices are formed by seamlessly stitched single crystal MoTe 2 domains (Xu et al., 2019a). Figure 2A shows the Raman spectrum of an as-grown MoTe 2 film, which presents the Raman characteristic peak of 2H-MoTe 2 at $235 cm À1 . Figure 2B shows the atomic force microscope (AFM) image of the MoTe 2 and the surface height profile along the white dashed line. The MoTe 2 is about 6 nm thick, corresponding to 9-layer MoTe 2 . The MoS 2 films ( Figure S1B) used in our devices are formed by single crystal MoS 2 domains (see the inset of Figure 2C). Figure 2C shows the Raman spectrum of an as-grown MoS 2 film, which presents Raman characteristic peaks of MoS 2 at $386 and $404 cm À1 (Li et al., 2012). The peak distance is $18 cm À1 , demonstrating the monolayer nature of the MoS 2 (Li et al., 2012).  iScience Article concentrations of the MoTe 2 and MoS 2 , enabling the realization of high-performance CMOS inverters (Figure S2). It is worth noting that, in order to avoid the ALD-caused n-type doping effect on the p-MoTe 2 , we also fabricated a CMOS inverter array with another device structure, where the MoTe 2 is free from Al 2 O 3 coverage ( Figure S4). The overall device performance did not improve ( Figure S5). Figure 3C shows the voltage transfer characteristics (VTCs) and voltage gain (ÀdV out /dV in ) plots of the inverter corresponding to Figures 3A and 3B. The inset is the CMOS circuit diagram. For each V dd applied (from 1 to 4 V), the VTC presents complete logic swing, and the maximum voltage gain is bigger than 1, satisfying the requirement for logic application. At V dd of 4 V, a maximum voltage gain of $23 and good noise margins (NM L z 0.40 V dd , NM H z 0.44 V dd , total noise margin z 0.84 V dd ) are obtained, indicating the potential of the CMOS inverter to be integrated into complex circuit systems . The noise margins for high input voltage (NM H ) and low input voltage (NM L ) are defined as NM H = V OH À V IH and NM L = V IL -V OL . V OH and V OL are the highest and lowest output voltages, respectively. V IH and V IL are, respectively, the higher and lower input voltages, at which the voltage gains of the VTC equal 1. The total noise margin is the sum of NM H and NM L . To evaluate the noise margins of our CMOS inverter, the input voltage range of the VTC is shifted to be symmetric with the output voltage range (Das et al., 2014). Figure 3D shows the power consumption (V dd 3 I dd ) characteristics of the inverter. At V dd of 1 V, peak power consumption of as low as $2.3 nW is achieved. Figures 3E and 3F show the VTCs and power consumption characteristics of another inverter (with MoTe 2 channel length of 15 mm). For each V dd applied (from 1 to 4 V), the VTC iScience Article also presents complete logic swing. At V dd of 4 V, a voltage gain of $9.5 and good noise margins (NM L z 0.36 V dd , NM H z 0.40 V dd , total noise margin z 0.76 V dd ) are obtained. Especially, ultra-low peak power consumption of $0.37 nW is achieved at V dd of 1 V. The statistical gain and power consumption data of the CMOS inverter array are presented in Figures S3A and S3B. It is worth noting that the peak power consumption (0.37-2.3 nW) of our inverters at V dd of 1 V is lower compared with previously reported CMOS inverters based on p-MoTe 2 and n-MoS 2 and among the lowest peak power consumption values reported so far for TMDCs-based CMOS inverters (see Table 1). Besides, all the inverters exhibit maximum voltage gains of >1 at each V dd applied.
We also investigated the dynamic switching behavior of the CMOS inverters. Figures 4AÀ4C show the time-dependent V out of an inverter (with MoTe 2 channel length of 10 mm) at V dd of 3 V, driven by square wave V in with various frequencies. The high and low levels of the input square wave were 0 and À6 V, respectively. Logic switching behavior is clear at 100 Hz and remains to be observed at a critical logic switching frequency of 1 kHz. The t r and t f are about 340 and 308 ms, respectively, at 1 kHz, calculated at 10% and 90% (marked by the red dashed lines in Figure 4B) of V out amplitude. The RC delays mainly result from the overlap capacitance in the CMOS circuit (Pezeshki et al., 2016;Wang et al., 2019). At 1.4 kHz, the amplitude of V out decreased to half ($1.5 V) of V dd , with t r (t f ) of about 275 ms (290 ms). The statistical dynamic switching frequency data of the CMOS inverter array are presented in Figure S3C.

Conclusions
We have fabricated CMOS inverter arrays using large-area CVD-grown p-MoTe 2 and n-MoS 2 . The current characteristics of the channel materials were balanced by atomic layer depositing Al 2 O 3 under proper conditions. Complete logic swing and clear dynamic switching behavior are observed in the inverters. The inverters have overall high performance such as maximum voltage gains of >1 at each V dd applied, low and even ultra-low peak power consumption (0.37-2.3 nW), and satisfying t r (t f ) and working frequencies. Our low-power-consumption CMOS inverters, with the merits of reproducibility and large-scale integration, have promising applications in future 2D microelectronic systems.

Limitation of the study
In order to further improve the device performance, developing new methods to increase the grain size of the monolayer MoS 2 is needed.

DECLARATION OF INTERESTS
The authors declare no competing interests.  iScience Article

Materials availability
This study did not generate new unique reagents.

Data and code availability
All data reported in this paper will be shared by the lead contact upon request.
This paper does not report original code.
Any additional information required to reanalyze the data reported in this paper is available from the lead contact upon request.

METHOD DETAILS
CVD growth of large-area MoTe 2 and MoS 2 Large-area MoTe 2 and MoS 2 films were grown via CVD method. For MoTe 2 growth, Mo films were deposited on SiO 2 (285 nm)/p + -Si substrates via magnetron sputtering. Then, the substrates were placed in a quartz boat containing Te powder. Molecular sieves were placed in the quartz boat between the substrates and the Te powder. After that, the quartz boat was pushed into the center heating zone of a quartz tube furnace with a tube diameter of 1 inch. After evacuating the quartz tube to an air pressure of less than 1 mTorr, high-purity Ar was let in at the maximum flow rate until the pressure reached atmospheric pressure. Next, the furnace was heated to 650 C in 30 min and kept there for 180 min. High-purity H 2 and Ar were used as carrier gases, whose flow rates were 7 and 5 standard cubic centimeters per minute (sccm), respectively. After the growth, the furnace cooled to room temperature naturally. For MoS 2 growth, SiO 2 (285 nm)/ p + -Si substrates were processed with O 2 plasma. After that, perylene-3,4,9,10-tetracarboxylic acid tetrapotassium salt (PTAS) was spin-coated on the substrates as seeding promoter. The substrates were placed in a quartz boat containing MoO 3 powder. Another quartz boat with S power was pushed into the upstream heating zone of a 3-temperature-zone quartz tube furnace with a tube diameter of 2 inch. Then the quartz boat with growth substrates was pushed into the downstream heating zone of the furnace. The growth was performed at atmospheric pressure. High-purity Ar (15 sccm) was used as carrier gas. The upstream and downstream heating zones of the furnace were heated to 200 C and 650 C, respectively, in 40 min, and kept there for 5 min. Finally, the furnace cooled to room temperature naturally.

Fabrication of the CMOS inverter arrays
Both the CVD-grown MoTe 2 and MoS 2 films were transferred with the help of PMMA and deionized water , and patterned into rectangular sheets through ultra-violet (UV) lithography and reactive