Machine learning thermal circuit network model for thermal design optimization of electronic circuit board layout with transient heating chips

This paper describes a method combining Bayesian optimization (BO) and a lamped-capacitance thermal circuit network model that is effective for speeding up the thermal design optimization of an electronic circuit board layout with transient heating chips. As electronic devices have become smaller and more complex, the importance of thermal design optimization to ensure heat dissipation performance has increased. However, such thermal design optimization is difficult because it is necessary to consider various trade-offs associated with packaging and transient temperature changes of heat-generating components. This study aims to improve the performance of thermal design optimization by artificial intelligence. BO using a Gaussian process was combined with the lamped-capacitance thermal circuit network model, and its performance was verified by case studies. As a result, BO successfully found the ideal circuit board layout as well as particle swarm optimization (PSO) and genetic algorithm (GA) could. The CPU time for BO was 1/5 and 1/4 of that for PSO and GA, respectively. In addition, BO found a non-intuitive optimal solution in approximately 7 minutes from 10 million layout patterns. It was estimated that this was 1/1000 of the CPU time required for analyzing all layout patterns.

does not easily fall into a local solution [32] [33], and its algorithm is provided as a programming library for ease of use. Therefore, BO may be effective for the CB layout optimization problem; however, its effectiveness has not been verified so far, to the best of the authors' knowledge.
In this study, BO is combined with a lamped-capacitance thermal circuit network model and applied to CB layout optimization problems, and its effectiveness is verified by comparing it with other algorithms (PSO and GA). Furthermore, the optimization is carried out based on unsteady state temperature simulations in which time variations of heating power and temperature of the components are considered. In the reported studies on CB layout optimization, the heating power of the heating components is assumed to be constant, and the layout optimization is performed using the temperature under steady-state conditions. However, in actual CBs, the heating power often varies with time. Therefore, the present study unveils the performance potential of BO in more complicated optimization cases than the reported studies. central semiconductor chip core (red-colored 1 node), which is the heat source, and its surrounding resin chip package (6 nodes).

Simulation model and problem setting
The thermophysical properties of the model components are summarized in Table 2. As shown in Fig. 2, it was assumed that the heating power of each chip varied with time. Each chip has different time-varying characteristics, and the total heating power, which is the sum of the heating power of each chip (black line), and peaks at t = 1047 s.  Because the lumped-capacitance model is used, the heat capacitance is connected to every node in Figure 1, although their circuit symbols are omitted in the figures. It is noted that the circuit symbols of thermal resistance between the nodes and the ambient air are also omitted. In LTCNM, the temperature at the nth node is calculated as: considering conduction and convection [36]. The initial and boundary conditions are listed in Table 3. This model was implemented in MATLAB/Simulink, and an unsteady heat transfer simulation was performed to obtain the temperature change characteristics of each node. The chip temperature is defined as the average temperature over the nodes within the chip component. Table 3  agreed well although the spatial resolution of temperature distribution of LTCNM is lower than that of FEM simulations.

Optimization problem setting
The target of the optimization is the CB layout, that is, the placement pattern of five transient heating chips A to E. In actual product design, there may be restrictions on chip placement depending on the functions of the devices. To simulate this situation, two restrictions on chip placement are given as i) placeable area for each chip and ii) distance between chips. In restriction i), each chip can only be placed in a mesh defined by a frame of the same color as the color of the chip symbol, as shown in Figure 3. In other words, each chip can only be placed within a specified area. In restriction ii), the distance between the nodes at the center of the chips must be less than or equal to the values shown in Table 4. For example, in Figure 4, the distance between chips A and B is 51.96 mm, which satisfies the restricted value (90 mm).  The optimization was performed so that the value of the following objective function f (x) was minimized: where x indicates one of the CB layouts. Tmean (t) is the mean chip temperature, that is, the average chip temperature over the five chips at time t; Thigh (t) is the highest chip temperature among the five chips at time t; max{} is the maximum value during

Applying Bayesian optimization
The thermal design optimization problem can be formulated as an optimization of the black box continuous functions f(x) as follows: where x is the input variable and f (x) denotes the objective function shown in Equation (3). The de-facto standard model for black-box optimization is the Bayesian optimization (BO) with a Gaussian process. Bayesian optimization (BO) is a popular framework for optimizing the black box function owing to its sample efficiency. The Gaussian process has been widely applied to solve real-world problems such as the prediction of thermal systems because of its ability to capture non-linearity and quantify uncertainty [43][44] [45]. Due to such characteristics, a Gaussian process is often selected to model the unknown objective function of BO. In BO, f (x) is a stochastic process, which is assumed to follow a Gaussian process, that is, the following equation (5) In this method, the posterior distribution of f (x) is calculated from the currently observed data based on Equation (5), and the next search point is determined using the acquisition function based on the information of the peripheralized predicted distribution. This process is repeated to find the optimal solution [46][47] [48]．The Matérn5/2 kernel [33] was used as well as an expected improvement (EI) [32] [33]. The combination of EI and the Matérn5/2 kernel is often used in practical applications [29]. In simulation, the "bayesopt" function of MATLAB library was used. Optimization with PSO and GA was also performed and compared with BO. The "particleswarm" and "ga" functions of the MATLAB library were used for PSO and GA, respectively. The hyperparameters of PSO and GA are shown in

Optimization results
Tables    shown. In Fig. 4(a), Tmean(t) reaches the maximum value at approximately t = 1200 s. This maximum value is the temperature of Chip A, which has the highest total heat generation, as shown in Table 1. In this case, because the chips should be evenly distancing to minimize f (x) = max{Tmean (t)}, it would be easy for us to predict a similar layout pattern intuitively. By contrast, in Fig. 4(b), with the optimization to minimize f (x) = max{Thigh (t)}, Chips B and C are arranged close to each other, and Chip A is mostly distancing from the other chips, which would not be easy for us to predict intuitively. This indicates that the optimized layouts are reasonable and that the thermal design optimization using BO, that is, a type of machine learning, is effective.

Applying BO to extended problem settings
In the actual thermal design of CBs, the number of layout patterns can be even greater. To test the performance of BO in such a case, BO was applied to an extended problem setting in which the restrictions i) and ii) described in section 2.2 are removed. In this case, the number of possible layout patterns is approximately 10 million. The optimization for f (x) = max{Thigh (t)} case was performed. Figure Table 6 in Chapter 4. Figure 6 shows that Chips A and B were optimized to maintain distance from the other chips. This is because the heating power of Chips A and B is relatively larger, as shown in Table 1, so they are placed farther distancing from each other to lower Thigh. Comparing the temperature trends in Fig. 6(c) and Fig. 4(

Conclusion
The lamped-capacitance thermal circuit network model combined with BO was applied to the layout optimization of an