Zero-sequence current suppression control for fault current damper based on model predictive control

In a multi-terminal direct current (MTdc) system based on a modular multilevel converter (MMC), high-speed and large interruption capability direct current circuit breakers (dc CBs) are required for dc fault interruption. However, commercializing these breakers is challenging, especially offshore, due to the large footprint of the surge arrester. Hence, a supplementary control is required to limit the rate of current rise along with the fault current limiter. Furthermore, the operation of the dc CB is not frequent. Thus, it can lead to delays in fault interruption. This study proposes the indirect model predictive control (MPC)-based zero-sequence current control. This control provides dc fault current suppression by continuously controlling the zero-sequence current component using circulating current suppression control (CCSC) and by providing feedback to the outer voltage loop and inner current loop of MMCs. The proposed control is simulated for pole-to-pole and pole-to-ground faults at the critical fault location of an MTdc system. The simulation is performed in Real Time Digital Simulator (RTDS) environment, which shows that the predictive control reduces the rate of rise of the fault current, providing an additional 3 ms after the dc fault occurrence to the dc CB to clear the fault. Besides, the energy absorbed by the dc CB’s surge arrester during the pole-to-pole and pole-to-ground fault remains the same with the proposed control.


Introduction
High power direct current transmission grid with a meshed modular multilevel (MMC) converter is considered a promising technology for extensive offshore wind power integration in Europe [1].Europe's expected new wind farm capacity of 116 GW during 2022-2026 [2].Based on submodules' (SMs) design and configuration, the MMC technology is classified into half-bridge (HB), full-bridge (FB), and Hybrid MMC [3].However, HB-MMCs are commissioned due to their lower footprint and cost.This comes up with another drawback: the need for direct current (dc) fault interruption capability.Unlike ac systems, dc systems do not have a natural current zero crossing during a fault period; therefore, a direct current circuit breaker (dc CB) is needed.Different dc CBs have been proposed, prototyped, and tested in the last decade for application in the MTdc systems [4][5][6].The dc fault interruption in HB-MMC-based MTdc systems has to be ultra-fast (< 3 ms) due to the high rate of rise of the dc current.In practice, to limit the fault current, the Fault Current Limiters, in the form of rectors, are added and used for dc fault detection [7].However, the high value of the inductance (> 150 mH) impacts the controllability of converters and increases the capital cost of the dc grid [8].
Another method to control the fault current is to regulate the pole-to-pole voltage near the converter, known as a Fault Current Suppression (FCS) method.In [9,10], a combination of hybrid-MMC and droop control is applied, which regulates the arm voltage as a way to decrease the fault current.A similar concept for an HB-MMC is used in [11,12].Furthermore, the authors also compared different methods of FSC.Similarly, [13] provides a soft current suppression control in the outer voltage loop.In [14], a notch filter is applied to extract the dc component and to regulate the fault current only during the fault occurrence.The suppression methods mentioned earlier imply proportional-integral (PI)-based control action, either in the outer voltage loop or by using a circulating current suppression control (CCSC).In [15], a suppression control was proposed for the FB-MMC MTdc using CSCC and a protection scheme.These controls are based on a mode selection during the fault; thus, the stability of these controls is undetermined [16,17].The fault interruption creates a temporary instability in the dc grid, propagating into ac systems where renewable energy resources are connected, which are more susceptible to disturbances.Hence, post-fault clearance is crucial.In the existing literature dealing with suppression control, MTdc systems are simplified for the offshore grid and its control for the offline simulation.Thus, the dynamics of the offshore grid is removed.The existing suppression controls are implemented with PI, which introduces inherent slower performance limitations [18,19].An optimization-based control like MPC demands high computation time.Thus, in literature, MPC-involved studies use offline simulation as the dependence on time is removed.In practice, the controller's control action must be in the acceptable time range.Hence, the real-time simulator provides us to investigate the same accept besides other advantages.The Hardware in Loop (HiL) setup indicates the physical connection of FPGA with the RTDS for the type 4 converter model as explained in [18].
In the CCSC, a zero-sequence component of -frame current representation can be viewed as one-third of the dc current (  ).However, in the traditional strategies, this current is either left uncontrolled [20] or employed in energy control [21].In this paper, we propose a controller for the mentioned zero-sequence current to decrease the fault amplitude and smooth the fault recovery.Furthermore, the model predictive control (MPC) has proven its superiority over conventional PI control in controlling complex non-linear, multiple-input multiple-output (MIMO) systems in different industrial sectors [22].
This paper introduces the indirect MPC-based zero-sequence current control employed for dc fault current suppression.The CCSC provides a reference to the outer voltage control (OVC) and direct voltage control (DVC).The proposed suppression control provides control during a dc fault, which regulates the fault current amplitude by reducing the rate of rise of the fault current.As a result, it provides an extra time margin for fault detection or dc CB breaker operation without affecting the circulating current suppression in the MMC arm.Additionally, better post-fault recovery is achieved.The proposed control can also be added to traditional PI control without creating system instability due to quadratic cost function formulation.Furthermore, the performance of CCSC is tested under different faults in the real-time digital simulator (RTDS) with the detailed equivalent models of the offshore wind farm, HB-MMC, and dc CBs.
In Section 2, the configuration of the MMC and the existing controls are analyzed.The proposed indirect MPC-based method is described in Section 3. The MTdc setup and the simulation results are elaborated in Section 4. Finally, meaningful conclusions are presented in Section 5.

MMC model and control
A decade of development in the modelling of MMCs has led to an accurate MMC non-linear model [19].The dynamics of the MMC can be formulated by using two components,  and , which represent the dc and ac characteristics of the converter, respectively.By applying the Clarke-Park transformation, the  and  ac components are translated into the stationary −frame: where and The definition of the zero-sequence component current is given with Eq. (1c).Its physical importance is actually its influence on the dc current since   = 3   .

MMC control design
In the MTdc, each onshore converter consists of three primary control loops [23], namely, OVC, inner current control (ICC) and CCSC, as shown in Fig. 1.Fig. 2 highlights the PI controls of the onshore and offshore converters.The OVC provides references to the ICC.The setpoints to the OVC are provided by the Dispatch level via TCP/IP communication interface, as it is shown in Fig. 1.The setpoint signals include dc voltage  , , ac voltage  , , active  , and reactive  , power, and frequency  .The selection of these signals depends upon the control mode (i.e.constant dc voltage, grid forming, activereactive power control-mode).Dispatch controls are typically operated by the system operators.The system operators provide the setpoint based on the power ac/dc power flow and day-ahead demand.
The ICC loop generates the modulating voltages (  , ) based on the feedforward terms (  , and   ).The ICC and OVC are only responsible for the fundamental and the odd-harmonic components of the ac grid current.The CSCC controls the dc and even harmonic components of the ac grid current.The presence of the even harmonic results in losses within the converter.Hence, these currents are suppressed by generating modulated voltage (  , ), and as a result, only the dc component is present.
The offshore converter consists of DVC and CCSC.The DVC is the simplest form of grid-forming control [23].Like onshore converters, the offshore converter receives setpoint commands from the dispatch control.Generated modulated voltages ( , , ) are then applied to lower level control (LLC), which comprises  −  transformation and sort and select submodule modulation.Traditionally, these controls are implemented using the PI controller by transforming ac measurements from the -frame into the stationary -frame using a phase lock loop (PLL) except grid forming control, which uses an oscillator [20].The control system of the type-4 wind turbines is the same as reported in [18].

MPC-based zero-sequence current control
As the name indicates, the MPC's prediction and accuracy are purely determined by the system's behaviour.The -frame mathematical model of the MMC is represented by Eqs. , and is rewritten in a matrix discrete form as: where Matrices  and  are defined as with   ∈ R as the sampling time, with value   = 40 μs.Furthermore, the augmented state is defined as , where ⃗ () ∈ R, represents system inputs.Similarly to [18], the future control sequence is represented by the discrete Laguerre network, ⃗  ∈ [−1, 1] 5 ⊂ R, which is determined by solving the optimal control problem, and minimizing the objective (cost) function, subjected to the equality and inequality constraints: Here,  ⪰ 0 and  ≻ 0 are weighting matrices, and   = 20 ∈ I + is the prediction horizon.For variables ⃗   (), vector () ∈ R 5 is a reference signal.The Matrix  and the column vector ⃗  are related to the constraint information of the rate, and amplitude [18].In reality, there will be an error due to the modelling or the signal noise.However, these disturbances can be considered in the optimal control problem, which is represented by ().With () is denoted the error between the system's measured signal and the plant's predicted signal at th instance.  ≻ 0 is the weight matrix.The reference determination of the differential-current components (denoted as   , ) remains the same as of the traditional control hierarchy as explained in Section 2.A.The CCSC mainly suppresses additive currents in the traditional control.However, the zero-sequence current component (   ) reference is left uncontrolled.The previous section explains that the MMC current on dc side can be represented by the zero-sequence current component.In this paper, zero-sequence current reference is calculated by using the active power injected/absorbed in the ac system and the dc voltage as shown in Fig. 3.
To reduce the dc fault current, one of the methods is to reduce the voltage across the dc CB line inductance (  ).The dc link voltage at the MMC terminals must be reduced to reduce the voltage across the dc CB line inductance.This decrease in the dc link voltage will further ) remains the same as the measured zero-sequence current (   ).Thus, no control action is provided by zero-sequence current control.However, during the dc fault period, the active power   increases, and the dc link voltage   decreases, which leads to saturation of the calculated zerosequence current.Hence, the zero-sequence current control provides the control action, which temporally reduces the dc link voltage.With the reduction in the dc link voltage, the rate of rise of fault current is reduced.Further, this control action is added to the outer voltage loop and direct voltage control in the case of grid forming converters (as shown in Fig. 3) to ensure that both ac and dc component values remain within the operating limits.

Experimental studies
The state-of-the-art model for the ±525 kV, 2 GW dc terminals is designed and simulated to demonstrate the proposed control advantages.The multiterminal dc grid adopted in this work is a modification of the benchmark model provided by Cigre's workgroup B4.74 [20].The following modifications are carried out in Cigre's workgroup B4.74: • The original benchmark model rated dc link voltage as ±500 kV.
However, the proposed dc-link voltage for the North Sea multiterminal dc grid is ±525 kV.Hence, the converter and control parameters had to change to meet this requirement.In addition to this, ac voltages offshore and onshore have to be altered based on the requirements.• The original benchmark model consists of 500 kV overhead transmission line connection, which needs to be replaced by the dedicated metallic return 525 kV submarine cables.Data for this cable have been adopted from an ongoing project.• The original benchmark model does not include offshore components like the wind turbine model, scaling transformer, and 66 kV submarine ac cable.Hence, based on the requirement, we changed the topology and included the offshore components.
Fig. 1 shows the simulated three terminals ±525 kV metal return bipolar MTdc system programmed for the real-time simulation in the RSCAD/RTDS.The system is divided into two zones (i.e., onshore and offshore).The onshore system consists of two converters (i.e., MMC1 and MMC3).Each platform is connected to two 1 GW MMC converters.The onshore platforms are connected to a strong grid, with a short circuit ratio of  = 44, by two converter transformers with a rating of 400∕275 kV, 1250 MVA.Similarly, the offshore platform has two 1 GW MMC converters connected to a wind farm via 275∕66 kV, 1250 MVA.This transformer also acts as a scaling transformer.The offshore platform is connected to the wind park by a 66 kV ac cable with a distance of 7 km.The ground for the MTdc is provided at the onshore platform with a resistance value of 0.01 Ω. Type 4 converter model (detailed equivalent model, implemented on FPGA) is used for MMC 1 and MMC 2, whereas MMC 3 is modelled as type 5 (averaged RTDS model) [23].The setup is comprehensively described in [18].The onshore zone is connected to the offshore zone by three 2 GW, 525 kV HVdc cables with the ratings given in Fig. 1.Cable 12 has two VSC-assisted resonant current (VARC) dc circuit breakers (CBs) at each cable's end.This VARC dc CB is scaled to 525 kV with a fault interruption capability of 20 kA [5].The wind park has nine Type-4 wind turbines, each with a rating of 2 MW at 16 m/s.Since this paper investigates dc system-level dynamics, the averaged model of a back-toback converter of a type 4 wind turbine is considered.This back-to-back converter is modelled using Descriptor State-Space (DSS) modelling approach [24].The grid side converter controls the dc link voltage of the type 4 wind turbine and provides reactive power support at the point of common coupling.In contrast, the machine side converter controls the torque and stator terminal voltage of the PMSM.The wind speed data is updated in real-time through a North Sea sensor using a python script [18].
Table 1 highlights the circuit parameters for the converters given in Fig. 1.The proposed controls are located in both offshore and onshore converters.In the onshore grid-tie converter station, MMC1 controls dc voltage (  , -mode), whilst MMC3 controls active power ( , -mode).The offshore converter MMC2 is a grid-forming converter (  ,  -mode).The data for the cable are adopted from the ongoing project [25].
In a steady state, MMC2 injects an active power of 2 GW into the dc grid generated by the wind power plant.MMC3 injects an active power of 1 GW into the onshore ac grid.In order to keep the dclink voltage constant, the remaining power is absorbed by MMC1 and injected into the onshore ac grid.Due to a full selective protection scheme being introduced [5], the internal protection of converters is disabled.The rated fault current interruption capability of the VARC dc CB is set to 20 kA, and the operating time of the dc CB is 5 ms.Furthermore, the dc fault detection is not instantaneous, so a 1 ms delay is introduced.Due to the multi-timestep simulation in the realtime simulator, the interested areas are modelled in small timesteps (2-3 μs) using processors and FPGAs.As a result, accuracy is maintained at an acceptable level.Since we investigate the control action by the proposed controller, this modelling accuracy is sufficient.

Fault amplitude identification
To identify the current hotspot in the MTdc during the fault, two different types of faults at two different cable locations are simulated.This work selects a positive pole-to-ground (PG) dc fault and a positive pole-to-negative pole (PP) dc fault.These faults are located at the MMC1's terminal (0%) and near the opposite terminal (100%).The nomenclature;   − 0 − 12 in Fig. 4 indicates the PG dc fault at the terminal in cable 12. Similarly,   − 100 − 12 indicates the PG dc fault at the opposite terminal of cable 12. Furthermore,  +  indicates the current measured in the cable  from  terminal of the cable.
Fig. 4 indicates the fault current measured at  = 6 ms without any fault current limiting scenario at different locations during different faults.The analysis shows that, for a given MTdc system at rated power, the PG and the PP fault near the MMC1 create fault currents with amplitudes 41.73 kA and 42.44 kA, respectively.Similarly, the fault near MMC2, on cable 23 produces the second highest fault current.The converters' pre-fault condition and the operating mode determine the fault current amplitude.Since MMC1 regulates the dc link voltage to a constant value, the fault near this terminal results in a high fault current.Similarly, the fault near MMC2 produces a high fault current due to the ac power infeed.Hence, the subsequent study considers the fault near MMC1 and MMC2 on cable 12.
To understand the impact of the proposed control strategies, the following cases are investigated: C1 Traditional PI control without zero-sequence current control.C2 MPC control without zero-sequence current control.C3 Traditional PI control with zero-sequence current control.C4 MPC control with zero-sequence current control.

Dc fault at MMC1's terminal
In this scenario, the PG and PP faults are applied at the terminal of MMC1.Furthermore, the impact of protection delay (i.e delay in fault detection or dc CB operation) (  ) is investigated for all cases and summarized in Tables 2 and 3. From these tables, it can be seen that the fault is interrupted by the dc CB with both traditional PI controls and MPC for   = 1 ms.Compared to PI control, during PG fault with MPC, the peak fault current in CB1P dc CB and MMC1 is lower by 0.7 kA and 1.26 kA, respectively.These lower values result from the MPC's fast control action on the state variables of MMC.However, this results in decreasing of dc link voltage at MMC1 ( ,1 ) by 16% compared with the rated voltage, which is referred as undershoot in this and subsequent sections.Furthermore, the settling time is increased by 50 ms.However, the fast control action helps the dc CB to absorb less energy.As the   increases, the peak amplitude of the fault current increases, and as a result, dc CB in the PI controlled system fails to interrupt.However, the MPC during the PG fault only adds up a surplus of 0.5 ms delay before the dc CB fails to interrupt the fault.A similar trend is observed with a higher fault current and undershoot in dc link voltage from rated voltage during the PP fault as shown in Table 3.
With the proposed control over    current, in PI's and MPC's CCSC, the sensitivity of the   is minimized to a greater extent.The system can withstand a higher delay, with a lower fault current in the converter and in the dc CB.This results in lower energy absorption in the dc CB's surge arrester during dc fault.The energy absorbed by the traditional PI-controlled MMC is 30% (PG) and 40% (PP) higher than that of the MPC-controlled MMC with the proposed control over    current for   = 3 ms during the PG and the PP fault, respectively.Furthermore, the settling time is shortened due to the active power feedback in the proposed control.However, a significant undershoot in  ,1 from rated dc link voltage is observed with the proposed control.It is also interesting to observe that the energy absorbed during the PG and PP fault interruption remains the same, indicating reduced stress on the surge arrester during the PP fault.As a result, an increase in   does not influence increase of the absorbed energy drastically. of fault current as seen Fig. 5(b).Furthermore, the proposed control prevents a large drop in converters' energy.Hence, it protects the sub-modules during fast transients.The arm currents of the converts are smaller compared to traditional PI-controlled MMC, as seen in Fig. 5(d).

Dc fault at MMC2's terminal
In this case, a PG and a PP fault are applied at the MMC2 terminal.The effect of protection delay is investigated for all cases and is summarized in Table 4 and 5, respectively.The dc fault near MMC2 creates a high rate of rise of fault current, which results in current interruption failure.The high value of d ,2 d is caused by the wind park's power infeed.Hence, MMC2 is very sensitive to the delay of the operation of dc CB, and the dc CB line inductance.However, with the application of the proposed zero-sequence current PI and MPC control, the delay sensitivity is removed for both types of faults as illustrated in Tables 4 and 5 for PP and PG faults.The energy absorption and the peak fault current through CB2P and MMC2 for both controls differ by less than 1%.The constant current source behaviour of the gridforming converters causes this.Moreover, on average, the settling time is improved by 100 ms in the MPC-controlled system.Furthermore, the undershoot in dc link voltage at MMC2  ,2 from rated dc link voltage during the PP fault is higher compared to the undershoot during the PG fault.

Conclusion
In this paper, a new MPC zero-sequence current control for the MMC converter is proposed, which influences the dc link voltage control.The proposed control method controls the additive zero sequence current component, and it can provide an extra window of 3 ms for fault detection or dc CB operation.This control is especially beneficial for a converter that directly influences the dc grid.The proposed control ensures the same energy absorption in the surge arrester during terminal PP and PG faults at the converter, which regulates the dc voltage of MTdc.The proposed controller can also be added to the existing PI-controlled converter.However, the slower nature of the existing PI control strategies cause a larger settling time of the dc link voltage.
There is a trade-off between the dc link voltage and the fault current.Based on the priority, suitable control constraints need to be set up.However, the implementation of this control reduces the time dependence on the protection algorithm, breaker operation, and fault current limiters by increasing the reaction time window.Hence, it provides more time for the proper reaction of the dc CB during the dc

Fig. 1 .
Fig. 1. Circuit and control hierarchy of Three terminal ±525 kV bipolar Mtdc simulated systems (The red dotted line indicates the ac-dc measurement).

Fig. 4 .
Fig. 4. Fault amplitude in kA at 6 ms for different fault types and locations in MTdc.

Fig. 5
highlights the significance of the proposed control compared to the PI and MPC in the time domain for PP fault.During the fault period, the MMC with the proposed control has d d of −114 kV/ms, while PI and MPC controlled MMC1 has d ,1 d of −40 kV/ms.The high value of d ,1 d creates a reduction in d ,1 d

Table 1
Circuit parameter for the simulated system.

Table 2
Performance of different cases under the pole-to-ground fault at the MMC1 terminal.

Table 3
Performance of different cases under the pole-to-pole fault at the MMC1 terminal.