Control system design for VSC transmission
Introduction
A voltage source converters (VSC) transmission system is generally similar to its predecessor HVDC transmission system where the main difference is the use of voltage source converters instead of line commutated converters (LCC). Because of the semiconductor technology constraints, VCS transmission is at present limited to lower power (around 300 MW), but it has already been implemented in a number of projects and it is likely to be further employed with higher voltage levels and in wider application areas [1]. The main advantage of VSC power transmission is the high controllability, the ability to control independently active and reactive power at each terminal and the possibility for linking with dead networks. These characteristics make VSC transmission attractive in many applications like the emerging interconnection with renewable energy sources. The disadvantages are known as higher power losses and higher capital cost compared with conventional HVDC [1], [2].
The converter topologies and their firing controls are in the development stage at many research centers, but it is widely believed that some form of pulse width modulation (PWM) control with two control inputs will normally be used. From a control system standpoint, a complete VSC transmission system has four control inputs, namely modulation signal magnitude and angle at each of the two converter stations. Because of the strong interactions among the control channels, it is a truly non-linear multiple-input multiple-output (MIMO) system.
Refs. [3], [4] propose a method for controlling VSC transmission based on a decoupling controller at each converter station. These methods use fast-feedback to linearise, decouple and simplify the feedback dynamics for d and q axis currents. The d–q current control reference inputs are further used for implementing P–V (or P–Q, or VDC–Q) control strategies at higher control level. Ref. [5] discusses the shortcomings of current measurement lag and further improves decoupling controller using an inner predictive control loop (for a UPFC test system). The possible issues with controllers [3], [4], [5] in VSC transmission are identified:
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Feedback linearisation/decoupling assumes that d–q axis currents and DC voltage signals are available at the bandwidth higher than the main control loops. In practice, these measurements are dependent on phase locked loop (PLL) output and they are noise contaminated which reduces the frequency range for accurate measurements. Consequently, this slows the main control loops. In ref. [5] predictive current controller improves speed but only for the reference inputs, the disturbance inputs rely on the current measurements.
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The control system in ref. [4] operates at three levels: at the fastest level is the feedback linearisation, then the main AC current loops and the DC voltage is the slowest outer control loop. Since the DC voltage is controlled in the outer control loop, during disturbances it can have poor responses in terms of overshooting and rise/settling times. On the other hand, DC voltage control is very important with VSC converters because of balancing issues since they are currently built of large number of small semiconductor units in series connection.
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The same current controller is used for system protection under faults. The current controller can regulate fault currents very well, but the control gains for fault conditions are detuned to enable equally satisfactory small-signal dynamics.
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Such controller design considers only the local converter dynamics. The dynamics of the DC line or the interactions between the two converters, which are important with VSC transmission, are not considered. This implies larger overshooting and slower responses as shown in ref. [3].
The aim of this study is to develop a fast VSC transmission controller with good DC voltage transient behavior at both converters, which also guarantees good stability and robustness properties. The controller should further enable current and voltage control during faults and fast fault recoveries.
The design is based on a small-signal linearised VSC transmission model developed earlier on MATLAB platform [6]. It is also desired to fully test the design for wide range of step inputs (reference and disturbance) and also for a range of typical fault scenarios, on a more accurate non-linear simulator.
The paper firstly reviews the analytical model for VSC transmission. The small signal design is presented in details in Sections 3 VSC transmission controller structure, 4 Fast controller design, 5 Slow regulating controller design, and the fault controller in Section 6. The controller is tested in Section 7.
Section snippets
The test system and modeling
The test system and the analytical MATLAB model are described in ref. [6] and only the summary is given here.
The test system is a 300 MW bi-pole VSC HVDC where only one pole (150 MW) is studied for simplicity. The system consists of a rectifier and inverter equivalent AC systems, the DC circuit and the controller as shown in Fig. 1, where the parameters are given in Appendix A. Each AC system has a typical short circuit level MVA of , corresponding to short circuit ratio SCR = SCL/PDC =
VSC transmission controller structure
The VSC transmission system is viewed as a multivariable four-input four-output plant. The control inputs and the system outputs are paired as it is shown in Table 1.
If a PI control is used with each of these control loops it is possible to achieve decoupled steady-state control and output regulation as it is shown in ref. [6]. The dynamic performance of such control system is however very poor, because of the strong interactions among the control loops. Only one of the control loops in such
Fast controller design
The fast controller has crucial influence on the stability, and the primary design goals are: good stability margins, good robustness for AC parameter changes at each AC system, and high performance regulation of the DC voltage. This design approach considers dynamics of the overall AC–DC–AC system, in developing the controller. We note that the considered AC–DC–AC system is complex, multivariable, higher order system (model is of 34th order), and also it is difficult to transmit on-line
Slow regulating controller design
The two fast control loops are primarily responsible for the system stability and the disturbance rejection/robustness properties. Since we are also interested in regulating the system outputs to the reference values we design PI controllers for the three loops: VACR, VACI and PDCR. These three loops do not require fast responses, they are not critical for stability, and their performance requirement is a zero-error output regulation with some reasonable settling time Ts < 400 ms.
The root locus
VSC transmission control under faults
The small signal controller in Sections 4 Fast controller design, 5 Slow regulating controller design is designed for the operation only around the steady state. Since this controller is based on fast DC voltage control, it would act as a firm voltage source and this would cause high over-currents during faults.
The controller for fault conditions has primary task of over-current reduction. The VSC transmission fault controller is inactive during the normal operation and it is designed to take
Steady-state controller
The designed system is simulated in PSCAD/EMTDC and a range of tests is performed. At the simulation stage the controller gains are tuned to final values, which are shown in Fig. 2. The new controller is compared against the decoupling predictive VSC converter as presented in ref. [5]. The predictive controller uses the same outer feedback loops as in Table 1, to enable comparison. It is labeled as predictive in figures in this section.
To simplify presentation the following curve labeling is
Conclusions
This paper presents a novel controller design for a VSC transmission system. The design is based on an accurate analytical model, enabling coordinated study of the overall AC–DC–AC system. It is postulated that system stability and good robustness can be achieved with two high-gain feedback loops: one at inverter side and another at rectifier side. The two control loops can be designed using a suitable MATLAB model, following the root locus rules and robustness indicators. The best fast
Acknowledgments
This project is supported by Department of Employment and Learning (DEL), Northern Ireland. The authors gratefully acknowledge the resources provided by AREVA T&D UK Ltd.–Power Electronic Systems.
Dragan Jovcic obtained a B.Sc. in Control Engineering from the University of Belgrade, Yugoslavia in 1993 and Ph.D. degree in Electrical Engineering from the University of Auckland, New Zealand in 1999. He is currently a lecturer with the University of Aberdeen, Scotland, where he has been since 2004. He also worked for the University of Ulster in period 2000–2004 and as a design engineer in the New Zealand power industry from 1999–2000. His research interests lie in the areas of control
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Dragan Jovcic obtained a B.Sc. in Control Engineering from the University of Belgrade, Yugoslavia in 1993 and Ph.D. degree in Electrical Engineering from the University of Auckland, New Zealand in 1999. He is currently a lecturer with the University of Aberdeen, Scotland, where he has been since 2004. He also worked for the University of Ulster in period 2000–2004 and as a design engineer in the New Zealand power industry from 1999–2000. His research interests lie in the areas of control systems, HVDC systems and FACTS. He is a member of IEEE.
Lisa Lamont obtained B.E. (Hons.) degree from University of Ulster, UK in 2001 and is currently studying for Ph.D. degree from the University of Ulster, UK. Her research areas of interest are FACTS and control systems. She is a student member of IEEE.
Keith Abbott obtained his B.Sc. (Hons.) in Electrical Engineering in 1966 and M.Sc. by research at the University of Newcastle-upon-Tyne, England.
He lectured from 1966 to 1981 at Sunderland Polytechnic in the Department of Electrical, Electronic & Control Engineering. From 1981 to 1997, he was head of department of Electrical & Electronic Engineering and associate dean of Engineering at Staffordshire University. Keith joined ALSTOM T&D Power Electronic Systems in 1997 and is currently manager of the Simulation and Studies Department, responsible for all ALSTOM's HVDC, SVC and STATCOM analysis. Keith has published 20 technical papers and is a Chartered Engineer, member of the IEE, Member of the IEEE and Member of CIGRE Working Group 38-14 Simulation of HVDC and FACTS.