A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA

Quantum-dot cellular automata, is an extremely small size and a powerless nanotechnology. It is the possible alternative to current CMOS technology. Reversible QCA logic is the most important issue at present time to reduce power losses. This paper presents a novel reversible logic gate called the F-Gate. It is simplest in design and a powerful technique to implement reversible logic. A systematic approach has been used to implement a novel single layer reversible Full-Adder, Full-Subtractor and a Full Adder–Subtractor using the F-Gate. The proposed Full Adder–Subtractor has achieved significant improvements in terms of overall circuit parameters among the most previously cost-efficient designs that exploit the inevitable nano-level issues to perform arithmetic computing. The proposed designs have been authenticated and simulated using QCADesigner tool ver. 2.0.3.

QCA F-Gate Adder Subtractor Adder-subtractor QCADesigner a b s t r a c t Quantum-dot cellular automata, is an extremely small size and a powerless nanotechnology. It is the possible alternative to current CMOS technology. Reversible QCA logic is the most important issue at present time to reduce power losses. This paper presents a novel reversible logic gate called the F-Gate. It is simplest in design and a powerful technique to implement reversible logic. A systematic approach has been used to implement a novel single layer reversible Full-Adder, Full-Subtractor and a Full Adder-Subtractor using the F-Gate. The proposed Full Adder-Subtractor has achieved significant improvements in terms of overall circuit parameters among the most previously cost-efficient designs that exploit the inevitable nano-level issues to perform arithmetic computing. The proposed designs have been authenticated and simulated using QCADesigner tool ver. Computational Simulation study has been used to determine results

Data accessibility
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Value of the data
Gates are the basic building block to design logic in digital systems. A new reversible F-Gate has been proposed to enhance the performance of digital systems.
Adder circuits are widely investigated since their performance can directly affect the whole digital system performance. We have proposed an optimal reversible Arithmetic circuits including Adder, Subtractor and Adder-Subtractor using the proposed F-Gate.
The presented circuit designs and data analysis can support the researchers to reduce the circuit complexity and implement high robust Arithmetic logic designs.
The proposed QCA reversible designs can be used to reduce hardware cost and design energy lossless arithmetic logic unit (ALU) in quantum computers.

Data
In this paper, a new high speed and a low power reversible gate called the F-Gate has been proposed. The logic symbol, QCA layout, and its simulation results are shown in Fig. 1. The proposed gate has been used in a systematic manner to implement single layer arithmetic logic functions such as reversible Full Adder (RFA), reversible Full Subtractor (RFS) and reversible Full Adder-Subtractor (RFAS). The logic symbol, QCA layout, and simulation results of the proposed Arithmetic circuits are shown in Figs. 2-4, respectively. A detailed report on the hardware costs achieved from the proposed QCA implementations in terms of area, cell counts and clock delays are provided in Table 1. However, the structural evaluation of the proposed RFAS circuit has been compared with their conventional counterparts [1][2][3][4][5]. The detailed comparison results of RFAS are shown in Table 2.

Experimental design, materials and methods
QCADesigner tool ver. 2.0.3 [6] with default parameters have been verified the functioning of the proposed QCA-circuits. The default parameters are listed as: QCA cell size ¼ 18 nm, diameter of quantum dots ¼ 5 nm, number of samples ¼ 50,000, convergence tolerance ¼ 0.001, radius of effect ¼ 65 nm relative permittivity ¼ 12.9, clock low ¼ 3.8e−23 J, clock high ¼ 9.8e−22 J, clock amplitude factor ¼ 2.000, layer separation ¼ 11.5 nm and maximum iterations per sample ¼ 100.
The simulation result, shown in Figs. 1-4, validates the functionality of the proposed circuits, which has used the proposed F-Gate as its main functional block.
The construction of the F-Gate is simple in design. It consists of three inputs (A, B, & C) and three outputs "P, Q, & R". The main processing part of the F-Gate is a three-input XOR (TIEO) [8]. The Q ¼ (A ⊕ B ⊕ C) is carried out from the main part of the F-Gate. The logic expression of inputs & outputs are expressed as: Q ¼ ðA⊕B⊕CÞ ð2Þ To testify the functionality of the F-Gate it has been used as a main component to compute Sum bits of the reversible Full-Adder (RFA), Difference of the reversible Full-Subtractor (RFS) and Sum/ Difference of the reversible Full Adder-Subtractor (RFAS). Table 2 includes a comparison between our proposed Full Adder-Subtractor with their conventional counterparts. An extensive structural analysis have been developed in different aspects of Area, Circuit complexity and cost of the proposed Full Adder-Subtractor and previously published works [1][2][3][4][5]. The proposed RFAS produce one garbage outputs. However, clock zones for wire crossing signal synchronization makes the latency (number of clock cycles), a little head greater than conventional designs. But the RFAS have achieved a significant improvements in terms of Cost ¼ Area × Delay × Power [7] than existing one. It performs both addition and subtraction operations. The main outputs of the RFAS circuit are, P ¼ A ⊕ B ⊕ C,