A high-level requirements engineering methodology for electronic system-level design

Abstract

Current electronic systems’ complexity severely limits their validation. Even if development frameworks keep improving and are heavily supported by the industry, methods for hardware/software electronic systems co-design are reaching a major crisis. Although the community is heading towards higher abstraction levels, requirements remain out of the validation scope. We therefore present a requirements engineering methodology that intersects formal, linguistic, and scenario views. Modeling consists in abstracting functionalities’ behaviours in terms of actions, expressed in a semi-formal structured language, later automatically translated in a pure formal notation. Such a mix makes the language accessible to designers and permits automation. Validation is then performed using consistency rules. Finally, an elicitation of missing functionalities is achieved using Boolean algebra.

Introduction

Hardware/software electronic systems co-design relies on a well-established cycle, through which designers employ mature development frameworks [1], [2], [3], [4] that have been deeply supported and improved over the years by industry. Despite such frameworks, hardware/software co-design is currently crossing the border of a major crisis: the size and complexity of current electronic systems that keeps growing deeply affects validation phases of the development process; formal techniques hit irreducible combinatorial explosions, while simulation-based procedures require painfully large execution times [10]. The community generally agrees that the design process must deal with descriptions expressed at higher levels of abstraction [5]. We especially believe that a key solution resides in the validation of requirements, i.e. ensuring that they respect certain quality standards such as consistency and completeness.

Although multiple validation methods are available along the design cycle, no methodology is provided for the validation of requirements. This relates notably to the lack of formalism in their expression. Indeed, the informal nature of requirements formulation typically prevents using systematic validation techniques, thus leaving them at the mercy of sporadic manually ad-hoc validation, or even no validation at all. Consistency errors can thus propagate through the design cycle, hence being detected only much later, with significant additional costs. Moreover, the gap between methods used to capture requirements and those used in the modeling phase is very large; designers usually jump directly from unstructured textual documentation (when they exist) to executable specifications written in languages such as Verilog [3]. Errors can thus easily be introduced during the production of the first executable model of some system.

Validating requirements may enhance their quality and, by transitivity, the quality of the modeling, that could result in a remarkable reduction of error detection costs. In addition, despite multiple validations occurring through the design cycle, some consistency errors may not be easily detected by traditional techniques, while an appropriate method could avoid them at the requirements stage. The development of adequate validation techniques for hardware/software requirements first necessitates a suitable formalism. This formalism must be accessible to designers. It must be light enough and avoid complex mathematical notations. At the same time, it must be formal enough to reduce the gap between requirements and executable models, as well as to permit automating the validation.

In this paper, we present a methodology relying on the application of requirements engineering principles to the hardware/software electronic systems co-design cycle. This methodology provides a solution for the modeling and validation of hardware/software electronic system requirements. By mixing linguistic and formal techniques, it provides a language that is both accessible to designers and formal enough to permit automatic validation. Modeling consists in describing system’s functionality using formally structured natural language constructs. These are then automatically translated into a pure formal representation, thus permitting automatic analysis. Validation is achieved using consistency rules. Finally, an elicitation of missing functionality is performed using Boolean algebra.

Our solution is meant to be grafted to the high-level and system-level electronic systems development cycle as shown in Section 5. It targets embedded systems that are composed of both software and hardware, such as systems on a chip (SoCs). Even if designated by the term “electronic systems”, the designing level of abstraction of such systems is far above gate-level electronic specifications.

Our team is, to our knowledge, the first to propose and develop such concepts to formalize and validate requirements for the hardware/software co-design field. The approach we propose allows designers to represent requirements using a common formalism. Moreover, it permits fast prototyping and early detection of consistency errors. We also target automatic derivation of test scenarios skeletons in order to bridge the gap between requirements and modeling levels.

Our main contribution with this paper is that it presents a requirements engineering methodology that can be easily grafted on top of current existing development cycles. This paper is organized as follows. Section 2 introduces the framework on which this research relies, including a review of existing works, in comparison to our approach. Section 3 presents our methodology, followed by Section 4 that presents relevant experimental results. Last, but not least, Section 5 presents on-going research that links our work with an existing UML-based methodology. Section 6 concludes the paper.