Effective work function control of metal inserted poly-Si electrodes on HfSiO dielectrics by in-situ oxygen treatment of metal surface
Introduction
As metal-oxide-semiconductor field-effect transistors (MOSFETs) are scaling down, the physical thickness of SiO2 and SiON gate dielectrics has dropped below 1.5 nm. The gate leakage current due to direct tunneling though the ultrathin oxides has increased significantly. Therefore, high-permittivity gate dielectrics (high-k gate dielectrics) are indispensable for gate dielectrics. In addition, metal gate electrodes are required to eliminate the gate depletion that inherent in conventional polycrystalline silicon (poly-Si) gates. The combination of metal gate electrode with high-k dielectrics is thus a promising candidate technology for further improvement of MOSFETs. When metal/high-k gate stacks integrated with a gate-first process, change in effective work function (EWF) after activation anneal is a serious concern, for p-FETs in particular [1]. This phenomenon, known as Fermi level pinning (FLP), is attributed to the formation of oxygen vacancy (Vo) in Hf-based dielectrics [2], [3]. Moreover, when reduction materials, such as carbon, are in the gate stacks, it turns out that formation of Vo is enhanced [4], [5]. Suppression of Vo formation in high-k dielectrics is the most important way to obtain the desired EWF.
Previously, we proposed a physical vapor deposition (PVD)-based in-situ method for fabricating high-quality metal/high-k gate stacks [6]. We formed Hf-silicate (HfSiO) dielectrics by utilizing the solid phase interface reaction (SPIR) between ultrathin PVD-grown metal-Hf layers (typically 0.5 nm thick) and SiO2 underlayers ranging in thickness from 1.3 to 1.8 nm [7]. Metal diffusion to the oxide underlayer induced by SPIR annealing forms high-quality HfSiO dielectrics, and the resultant equivalent oxide thickness (EOT) is smaller than that of the initial oxide thickness of SiO2 underlayer. To precisely control the formation of interface silicate and reduce the impurities in the gate stacks, in-situ SPIR annealing was done without exposure to air using a cluster tool that consists of low-damage PVD equipment and an annealing module [6]. After the gate dielectrics formation, the wafers were transferred back to the PVD chamber to continuously deposit thick TiN electrodes by reactive sputtering using a Ti target and a N2/Ar gas mixture. By using this process, we reduced the carbon impurities in the gate stacks, and reduced the threshold voltage (Vth) and obtained excellent electrical properties for gate-first p-MOSFETs [8], [9]. Recently, for the gate-first process, the thickness of metal gate reduced under 10 nm and thick poly-Si electrode is formed on the metal gate in general, which is known as metal inserted poly-Si stack (MIPS) structure. MIPS approach is widely accepted because of its compatibility with the conventional complementary MOS integration schemes. However, with the poly-Si/TiN/HfSiO/SiO2 gate stacks, we found that formation of Vo in high-k dielectrics were enhanced by Si diffused into TiN electrode from poly-Si layer after high temperature annealing, as shown in Fig. 1. To suppress Si diffusion from poly-Si layer after high temperature annealing, we fabricated poly-Si/TiON/HfSiO/SiO2 gate stacks by utilizing an in-situ PVD method and oxide layers formed on the TiN surface as a result of exposure to air. As a result, we suppressed Si diffusion after high temperature annealing [4]. We considered that TiOx formed on the TiN electrode surface by exposure to air worked as a Si diffusion barrier layer as shown in Fig. 1. When we investigated electrical properties of the gate stacks, we obtained high EWF and FLP recovery after high temperature annealing [4]. However, the oxidation method of the TiN electrode surface by the air-exposure process has poor controllability and productivity.
In this study, we fabricated novel poly-Si/TiN/HfSiO/SiO2 gate stacks by using in-situ oxygen treatment process of TiN electrode surface before poly-Si deposition to suppress Si diffusion from the poly-Si layer. We investigated Si diffusion into TiN electrode by using back-side secondary ion mass spectrometry (BS-SIMS) and electrical measurements after high temperature annealing.
Section snippets
Experimental procedure
In this study, we fabricated poly-Si/Ti(O)N/HfSiO/SiO2 gate stacks by utilizing PVD based in-situ method. Fig. 2 shows process flow for the in-situ fabrication method. We used 1.8-nm-thick SiO2 underlayers prepared by conventional rapid thermal oxidation (RTO) of p-type Si wafers. A 0.5-nm-thick metal Hf was then deposited by low-damage DC sputtering. HfSiO dielectrics were formed by in-situ annealing at 850 °C for 1min at 10−3 Torr oxygen pressures. A 10-nm-thick TiN electrode was subsequently
Results and discussion
Depth profiles of Si atoms in the gate stacks before and after PDA treatment at 900 °C for 30 s in N2 ambience in the reference and in the oxidized samples are shown in Fig. 3 as well as the result of TiN of the reference sample. Here, Si diffused into TiN electrode after FGA only for the reference sample. Furthermore, Si diffusion into the TiN electrode was more remarkable after PDA treatment at 900 °C. On the other hand, the oxidized samples had negligible Si-diffusion even after high
Conclusions
We investigated the formation of Si diffusion barrier layer by an in-situ oxygen treatment process of TiN electrode surface prior to poly-Si deposition. As a result, we found suppression of Si diffusion from poly-Si layer into TiN electrode after high temperature annealing. Moreover, we obtained a high EWF of 4.94 eV after high temperature annealing at 1000 °C. However, significant growth of interfacial SiO2 occurs in parallel with increasing EWF. From a theoretical study based on chemical
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