A low-voltage wide-input CMOS comparator for sensor application using back-gate technique

doi:10.1016/j.bios.2003.10.013

Biosensors and Bioelectronics

Volume 20, Issue 1, 30 July 2004, Pages 53-59

https://doi.org/10.1016/j.bios.2003.10.013 Get rights and content

Abstract

In this paper, two new analog CMOS comparators (Type-I and Type-II) with low-voltage and wide-input capabilities are proposed. The comparator receives two analog inputs and puts out one digital state to identify the larger (or the smaller) of the input variables, which represents an useful operation in data conversion and sensory signal processing. Without using special fabrication technologies, the supply voltage of the circuit is reduced to 1 V. Due to the utilization of CMOS back-gate technique, the input range of the comparators is greatly improved. The comparators are composed of bulk-driven stage and dynamic latch. By using a CMOS n-well technology, the results of HSPICE simulations indicate that the response time of Type-I circuit is 1 μs under 10 mV identified resolution. Type-II comparator achieves 5 mV identified resolution. The input dynamic ranges of the comparators are approximately rail-to-rail.

Introduction

The comparator is an import element in signal processing systems, such as telecommunication interfaces, analog-digital converters, as well as in the sensory circuits. Precision, speed, power consumption, input range, and chip area must be noticed for a comparator design. Since CMOS integrated circuit fabrication is continuously improving, via thinner gate oxides, reduced device size, and so forth, the voltage supply of VLSI circuit in sub-micron technologies must be reduced. Furthermore, portable battery-operation equipments such as biomedical electronics and telecommunication equipments are common applications recently. Thus, design of a low-voltage low-power comparator is an important research. Many high-performance comparators have been proposed (Wu and Wooley, 1988, Yin et al., 1992, Atherton and Simmonds, 1992, Razavi and Wooley, 1992, Laug et al., 1992, Bruccoleri and Cusinato, 1996, Shih et al., 1997, Cusinato et al., 1998, Kotani et al., 1998, Boni et al., 2000). Research work for these comparators has focused on offset cancellation, high-operating speeds, and high-accuracy requirements, yet all of them operate in a supply range of 3–5 V. In open literature, designs of low-voltage comparators are also proposed (Abo and Gray, 1999, Terada et al., 2000, Waltari and Halonen, 2001, Fayomi et al., 2001, Rombouts et al., 2001, Hung and Liu, 2003). However, the reliability, the input range, and the speed of these comparators must be further improved for biosensor’s application. Due to the low-voltage requirement, this paper proposes two 1 V wide-input CMOS comparators without using special technologies. Since no extra fabrication mask is required, the fabrication cost is reduced.

Section snippets

CMOS back-gate technique

For a low-voltage VLSI circuit design using a common CMOS fabricated process, one of the major problems is the threshold voltage. Although the CMOS transistor is a four terminals device, the n-well (or n-substrate) terminal is often connected to the positive voltage and the p-well (or p-substrate) terminal is connected to the negative voltage. Using the three-terminal MOS transistor, a commonly used schematic for sensor applications is shown in Fig. 1. The sensor signal drives the gate of the

Type-I: simulation results

By using a 0.5-μm double-poly double-metal n-well CMOS technology, an experimental comparator was designed. With a V_DD of 1 V, various input voltages were applied to test the comparator’s precision and input range. The inputs, at each 1 μs per voltage level, were: $V_{in1} (t)=(0.00 V,0.11 V,0.30 V,0.51 V,0.70 V,0.91 V,0.99 V)$ and $V_{in2} (t)=(0.01 V,0.10 V,0.31 V,0.50 V,0.71 V,0.90 V,1.00 V).$ The clock high was 1 V (V_DD). The periods of the clocks φ_rst, φ_cmp, and φ_lat were 1 μs with a 75, 50, and 25% duty cycles,

Conclusion

Without using a special fabrication technology, the design of two wide-input comparators working at a 1 V supply voltage is presented, which uses back-gate and clock-boosted techniques. By simulation, Type-I and Type-II comparators are able to distinguish a 10 and 5 mV difference within 1 μs, respectively. These low-voltage wide-range comparators are suitable for small signal processing. Importantly, the comparator is easily integrated within low-voltage system-on-chip (SoC) applications.

Acknowledgements

This work was supported by the Chip Implementation Center, and the MOE Program for Promoting Academic Excellence of Universities under Grant EX-91-E-FA09-5-4.

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A low-voltage wide-input CMOS comparator for sensor application using back-gate technique

Abstract

Introduction

Section snippets

CMOS back-gate technique

Type-I: simulation results

Conclusion

Acknowledgements

A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter

IEEE J. Solid-State Circuits

An offset reduction technique for use with CMOS integrated comparators and amplifiers

IEEE J. Solid-State Circuits

Dynamic characterization of high-speed latching comparators

Electron. Lett.

Offset reduction technique for use with high-speed CMOS comparators

Electron. Lett.

Analysis of the behavior of a dynamic latch comparator

IEEE Trans. Circuit Syst.-I

1-V CMOS comparator for programmable analog rank-order extractor

IEEE Trans. Circuit Syst.-I

CMOS charge-transfer preamplifier for offset-fluctuation cancellation in low-power A/D converters

IEEE J. Solid-State Circuits