With every new CMOS technology node today, pure analogue design becomes more difficult, digital design more analogue, and RF design more feasible. Enabling new possibilities, such as RF-CMOS, while extending old ones is the challenge future technologies are facing.
Traditionally analog features, such as matching and cross-talk, are now entering the digital domain e.g. in Static Random Access Memories (SRAM) and clock tree design. Device and interconnect (compact) models must be able to cope with new technology steps like pocket implants and copper Damascene, while extending their capabilities for analogue and RF e.g. by modelling Non-QuasiStatic (NQS) effects. The System-on Chip (SoC) demand requires a multitude of high performance functionality's to be combined on one piece op silicon. It is obvious that this will lead to very complex processes. Finally, technology scaling, and the ever increasing pressure on specifications, have triggered multi-die packages and Silicon-On-Anything (SoA).
