Design and fabrication of planar guard ring termination for high-voltage SiC diodes
Introduction
Silicon carbide has gained a substantial increase in research interest over the past few years as a base material system for high frequency and high power semiconductor devices. 4H-SiC is the most attractive polytype for power devices due to its wide band gap (3.2 eV), high mobility , excellent thermal conductivity , and high critical field strength (∼). Important for power devices, the 10× increase in critical field strength of SiC allows high voltage blocking layers to be fabricated significantly thinner than for comparable Si devices. This reduces device on-resistance, while maintaining the same high voltage blocking capability. Numerous SiC high power switching devices such as GTOs [1], [2], MOSFETs [3], [4], pn diodes [5], [6], [7], and Schottky diodes [8], [9], [10], [11] have been demonstrated with results approaching or exceeding the theoretical limits of Si.
Limiting the potential performance of SiC power devices, however, is the relatively immature development of proper edge termination. As is widely known, high-voltage planar junctions under reverse bias exhibit significantly lower breakdown voltages than one-dimensional theory predicts due to 3-D effects of field crowding at the junction periphery [11]. Specialized edge termination structures must be used to minimize this effect and increase the planar junction breakdown voltages to near ideal values. SiC edge termination is thus critical in order to obtain maximum breakdown voltage and correspondingly minimum on-resistance.
Several different edge termination methods for SiC planar pn junction termination have previously been investigated, field plate extensions [10], junction termination extensions (JTE) [5], [8], [12], and high-resistivity implanted layers [13]. Field plate structures suffer from an enhanced oxide field near the field plate edge due to the increased critical field strength of SiC, which can result in serious reliability concerns when scaled to higher voltages. JTE methods have produced good results in SiC devices, but often require additional processing steps and precise knowledge of net implant activation percentage.
The floating guard ring structure (Fig. 1) has been widely used in Si technology as an effective means of planar edge termination [14], [15]. It is an attractive method of edge termination since it is usually formed simultaneously with the main junction or anode contact, thus saving costly processing steps. The guard ring structure serves to reduce the amount of field crowding at the main junction by spreading the depletion layer past consecutively lower potential floating junctions (rings). A ring becomes biased when the spreading depletion layer punches through to the floating junction. To remain in equilibrium, the ring’s potential will follow that of the surrounding material to within the built-in potential of the junction. These independent junctions act to increase the depletion layer spreading, thereby decreasing the high electric field at the main junction. Optimized designs have the electric field shared equally among the main junction and floating rings.
Silicon guard ring planar junctions are predominantly formed by deep diffusion of impurities, which results in a large cylindrical junction radius (xj). It has been shown [15] that if xj is large in comparison with the critical depletion width (Wcpp), the effects of electric field crowding can be reduced. Additionally, if the ratio of xj/Wcpp is large, optimum ring spacing becomes larger and equally spaced guard rings becomes more effective [16]. This lessens the need for rigorous numerical simulation solutions. Unfortunately, because of the high Si–C bond strength, planar junctions in SiC can only be formed through implantation. Even at high energies, lattice damage and implant time constraints limit junction depths to about 2 μm. For high voltage blocking layers, the rj/Wcpp ratio becomes small, strongly increasing the need for precise ring spacing. We have used numerical simulations to optimize the guard ring spacing for maximum breakdown with minimal area consumption.
Section snippets
Guard ring design
The optimization of floating guard ring structures is extremely complex, with the results being strongly coupled to both solution method and grid conditioning [17]. To simulate the potential in the floating guard rings, the hole quasi-Fermi potential must be calculated independently for each p+-floating ring. Therefore, a coupled solution of both Poisson’s equation and both current continuity equations must be used for accurate results.
Simulation results obtained for planar junctions using
Device fabrication
Our optimized floating ring design was experimentally verified with implanted pn diodes fabricated on high quality n+ Cree wafers. The n-type epi-layers were grown at Auburn University by chemical vapor deposition at 1500°C on square pieces of n+-doped 8° off-axis 4H-SiC substrates obtained from Cree Research Inc. The thickness of the epi-layers was approximately 10 μm, with a constant carrier concentration of obtained by CV profiling. The p+ anode junction and guard rings
Results and discussion
As predicted by simulation, the experimental results for the diodes with implanted guard rings showed a significant improvement in breakdown voltage over those without edge termination. Measurements were made using a Tektronix 371 curve tracer in conjunction with a HP Picoammeter, with the samples immersed in a Flourinert™ solution.
The measured breakdown, normalized to the ideal parallel plane value, is plotted in Fig. 6 for diodes with variable one and two guard ring spacings along with the
Summary
We have demonstrated the effective design and implementation of a multiple floating guard ring structure for SiC planar junctions. Breakdown voltages reaching 80% of the ideal parallel plane value were predicted. The high measured breakdown values for these optimized structures is comparable to other reported SiC edge termination techniques, but requires fewer processing steps and is easily transferable to other SiC power devices. Simulated results have also shown that the small inter-ring
Acknowledgements
This work was supported by the Center for Space Power and Advanced Electronics, located at Auburn University, under NASA Grant NAGW-1191-CCDS-AD. The authors would like to thank Professor John Williams of Auburn University, Dr. John Crofton of Murray State University, and Dr. Jeff Casady of Mississippi State University for insightful discussions on SiC implants and contacts.
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