Performance improvement of polycrystalline thin-film transistor by adopting a very thin amorphous silicon buffer

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Abstract

A novel polycrystalline thin-film transistor (TFT) with a very thin (<10 nm) a-Si:H buffer has been studied. The off-state leakage current of the coplanar polycrystalline silicon (poly-Si) TFT was reduced using quadruple layers of a-Si:H, SiNx, thinner a-Si:H and poly-Si and by simultaneous silicide formation of the source, drain and gate contacts. While offset-gate and lightly doped drain (LDD) poly-Si TFT structures require additional mask steps to form the field-reduced regions, the proposed poly-Si TFT needs only 2 photo-mask steps. The on–off current ratio increases from 106 to 108 by adopting a thinner a-Si:H buffer on the poly-Si.

Introduction

Polycrystalline silicon (poly-Si) thin film-transistors (TFTs) offer the capability to integrate driver circuitry directly onto glass substrates. However, the leakage current of these devices is critical when they are applied to pixel switching devices of active-matrix liquid–crystal displays (AM-LCDs), since their leakage current decreases the voltage holding ratio of the pixels [1].

Offset-gate and lightly doped drain (LDD) are commonly used structures to reduce leakage current in poly-Si TFTs. However, conventional LDD and offset TFTs need additional mask steps to form the field-reduced region. That is, the formation of the lightly-doped n region complicates processing and increases production cost. These structures feature drain field-reduced regions between gate and drain electrodes since the main mechanism of leakage current is the field-assisted electron tunneling from the valence band to the conduction band via the trap states in the poly-Si.

In our previous study, we developed an a-Si:H coplanar TFT [2], a poly-Si TFT with a SiNx gate insulator [3] and a poly-Si TFT with Ni–silicide source/drain contacts [4]. For an a-Si:H coplanar TFT of the same structure as the coplanar poly-Si TFT, the measured leakage current was sufficiently small although the self-aligned coplanar structure has a larger electric field in the drain region. This effect can be explained by the greater band gap of the a-Si:H. Note that the band gap (1.9 eV) of a-Si:H is larger than that (1.1 eV) of poly-Si.

In this study, the greater band gap a-Si:H was introduced to reduce the leakage current of a coplanar poly-Si TFT. To achieve a lower interface state density with the a-Si:H, SiNx produced by plasma enhanced chemical vapor deposition (PECVD) was used as the gate insulator-material. To simplify the fabrication process and obtain better performance, silicide electrodes for S/D contacts were employed [5]. The off-state leakage current of the proposed poly-Si was of a sufficiently small level despite using a self-aligned structure which inevitably has a larger drain-field region.

Section snippets

Experimental

Fig. 1 depicts a cross-sectional view of the fabricated TFT. The fabrication process of the poly-Si TFT with an a-Si:H buffer was as follows: First, a 50 nm thick a-Si:H layer was deposited by PECVD and then crystallized by excimer laser annealing (ELA). On the ELA poly-Si, 4–10 nm thick a-Si:H buffer was deposited by PECVD at a substrate temperature of 160°C and a rf power of 50 W. Note that the a-Si:H buffer is deposited at lower temperature and smaller rf power than those for the active

Results and discussion

Fig. 2 shows the field effect mobility (μeff) and the minimum Id for the poly-Si TFTs with a-Si:H deposited at different substrate temperature. Both Id and μeff increased with increasing temperature, which is presumably due to the fact that the deposited silicon on the poly-Si has increased microcrystalline phases as the temperature and the rf power increase [6].

Fig. 3 shows the transfer properties for the poly-Si TFTs with three different structures of self-aligned, LDD and a-Si:H buffered.

Conclusions

The off-state leakage current of poly-Si TFTs was reduced by using a thin a-Si:H buffer on top of the active layer. The main mechanism of the reduction in the off-state current is the larger band gap property of a-Si:H near the channel region. A poly-Si TFT with a 10 nm thick a-Si:H buffer had a field-effect mobility of ∼12 cm2/Vs, a threshold voltage of 3.55 ± 0.05 V, a sub-threshold slope of ∼0.89 V/dec, an on/off ratio of ∼108 and off-state leakage current of 3 fA/μm at VD=1 V and VG=−5 V.

Acknowledgements

This work was supported by the Electronics and Telecommunications Research Institute and the Ministry of Information and Communications, Korea.

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