Stress analysis of stacked Si wafer in 3D WLP

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Abstract

In 3D wafer-stacking technology, one of the major manufacturing issues is wafer warpage because it causes process and product failures, such as delamination, cracking, mechanical stresses, and even electrical failure. In this study, the wafer warpage and local strain of thinned Si wafers in a wafer stack were investigated. A blanket Cu film was deposited on a Si wafer by a sputtering process. Two Cu deposited wafers were bonded by a thermo-compression method, and a stacked wafer was thinned down to 30 μm. The three wafers were then stacked on a Si wafer substrate. The wafer warpage and local strain of each stacked Si wafer were measured by film-stress measurement and the convergent-beam electron diffraction technique of transmission electron microscopy, respectively. An emphasis was placed on the effects of wafer stacking by Cu bonding and Si thinning on stress development in a thinned Si wafer. As the number of wafers in a stack increased, wafer warpage became severe, and the local strain in thinned Si wafers near the Si/Cu interface was increased.

Introduction

Three-dimensional wafer level packaging (WLP) has been developed extensively as a next-generation microsystems packaging solution. While 3D technology promises outstanding benefits in terms of performance, size, and cost, it must overcome several challenges in the areas of design, architecture, power, heat, and processing [1]. There are also other integrated problems in manufacturing including the wafer warpage issue of stacked wafers. Wafer warpage is becoming a critical problem which needs to be resolved because it causes process and product failures, such as delamination, cracking, mechanical stresses, and even electrical failure [2].

In addition to a global warpage issue on a wafer level, there is a local device issue on a transistor level due to strained silicon. It is well known that tensile stress improves nMOS devices and compressive stress improves pMOS devices [3]. There are many studies on the use of strained silicon to improve device performance [3], [4], [5]. In 3D WLP, the stacking of wafers produces mechanical stresses on a wafer globally and locally because of repetitive bonding and thinning processes.

In this study, the wafer level curvature of a thinned Si wafer in a wafer stack was evaluated by a film-stress measurement (FSM) system, and the local level strain of each thinned Si wafer at the near Si/Cu interface was investigated by the convergent beam electron diffraction (CBED) technique of transmission electron microscopy (TEM). The effects of wafer stacking by Cu bonding and Si thinning on the stress development in thinned Si wafers were studied.

Section snippets

Fabrication of stacked wafers

Si wafers with a 6 in diameter were used as a substrate, and sputtered Ta/Cu was used as a bonding material. After depositing a 0.35 μm-thick layer of Ta/Cu on a Si wafer, Cu bonding was performed at 400 °C under pressure of 35 KN for 60 min using a thermo-compression wafer bonder (EVG 520-HE). After bonding, the top Si wafer of the stack was thinned down to about 30 μm using a wafer grinder (DISCO, DGP8760). Then, the thickness of the thinned Si wafer was measured by Fourier transform infrared

Results and discussion

Fig. 3 shows the wafer curvature of each wafer stack obtained by FSM. It was found that the maximum wafer bow became severe as the number of wafer stacks increased, but the increment of maximum wafer bow was reduced as the number of stacks increased. Both the CTE mismatch between Si(2.3 ppm/°C) and Cu(16.7 ppm/°C) and the thickness of the thinned Si influenced the wafer curvature of wafer stack [2]. Since the wafer edge had a severe bow, the CBED samples were prepared from the wafer stack edge.

Conclusion

The effects of wafer stacking on the stress development in thinned Si wafers were studied using the CBED/TEM technique. The lattice parameters were estimated from the local strain measurements for each thinned Si wafer in a wafer stack. It was shown that wafer warpage could significantly affect the local strain in thinned Si wafers. As the number of wafers in a stack increased wafer warpage became severe, and the local strain in thinned Si wafers at the near Si/Cu interface was increased.

Acknowledgments

This project was conducted through the Practical Application Project of Advanced Microsystems Packaging Program of Seoul Technopark, funded by the Ministry of Knowledge Economy.

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