Truly random number generators based on a non-autonomous chaotic oscillator

https://doi.org/10.1016/j.aeue.2006.05.006Get rights and content

Abstract

A non-autonomous chaotic circuit which is suitable for high-frequency integrated circuit (IC) realization is presented. Simulation and experimental results verifying the feasibility of the circuit are given. We have numerically verified that the bit streams obtained from the stroboscopic Poincaré map of the system passed the four basic tests of FIPS-140-2 test suite. We also have verified that the binary data obtained from the hardware realization of this continuous-time chaotic oscillator in the same way pass the full NIST random number test suite. Then, in order to increase the output throughput and the statistical quality of the generated bit sequences, we propose a TRNG design which uses a dual oscillator architecture with the proposed continuous-time chaotic oscillator. Finally, we have experimentally verified that the binary data obtained by this oscillator sampling technique pass the tests of full NIST random number test suite without Von Neumann processing for a higher throughput speed while compared with the previous one where the proposed continuous-time chaotic oscillator is used alone.

Introduction

Nowadays, because of the increasing demand of electronic official and financial transactions and digital signature applications, the need for information secrecy has raised. In this manner, random number generators (RNGs) which have been used for only military cryptographic applications in the past got expanding usage for a typical digital communication equipment.

Almost all cryptographic systems require unpredictable values, therefore RNG is a fundamental component for cryptographic mechanisms. Generation of public/private key-pairs for asymmetric algorithms and keys for symmetric and hybrid cryptosystems require random numbers. The one-time pad, challenges, nonces, padding bytes and blinding values are created by using truly random number generators (TRNGs) [1]. Pseudo-random number generators (PRNGs) generate bits in a deterministic manner. In order to appear to be generated by a TRNG, the pseudo-random sequences must be seeded from a shorter truly random sequence [2]. Random numbers are also used during the authentication procedure between two cryptoequipments and initial value randomization of a cryptomodule that realizes an algorithm.

Even if RNG design is known, any useful prediction about the output cannot be made. To fulfill the requirements for secrecy of one-time pad, key generation and any other cryptographic applications, the TRNG must satisfy the following properties: The output bit stream of the TRNG must pass all the statistical tests of randomness; the next random bit must be unpredictable; the same output bit stream of the TRNG must not be able to reproduced [3]. The best way to generate truly random numbers is to exploit the natural randomness of the real world by finding a random event that happens regularly [3]. Examples of such usable event include elapsed time during radioactive decay, thermal and shot noise, oscillator jitter and the amount of charge of a semiconductor capacitor [2].

There are few integrated circuit (IC) RNG designs reported in the literature; however, fundamentally four different techniques were mentioned for generating random numbers: amplification of a noise source [4], [5], jittered oscillator sampling [1], [6], [7], discrete-time chaotic maps [8], [9], [10], [11] and continuous-time chaotic oscillators [12], [13]. In spite of the fact that, the use of discrete-time chaotic maps in the realization of RNG is well-known for some time, it was only recently shown that continuous-time chaotic oscillators can be used to realize TRNGs also. Following up in this direction, we investigated the usefulness of the proposed chaotic oscillator as the core of a RNG.

Although many chaotic oscillators exist in the literature, only a few of them are designed concerning high-performance IC design issues, such as low power consumption, high-frequency operation and operation capability at low voltage levels [14]. In this work, we present a simple non-autonomous chaotic oscillator, which is suitable for high-performance IC realization.

Initially, we have obtained random data from the stroboscopic Poincaré map [15] of the proposed chaotic system and numerically verified that the bit streams generated from the random number generator built around the proposed circuit pass the four basic random number tests of FIPS-140-2 test suite [16]. Moreover, we have also experimentally verified that the binary data obtained from the chaotic circuit pass the tests of NIST full random number test suite [17].

Substrate, ground, power supply and clock signal interference are a major concern in RNG design since interfered and random signals have comparable levels and this may cause to reduce the statistical quality of the output sequence. To solve this problem, in [18], a TRNG which mixes three of the four mentioned RNG techniques except for the continuous-time chaos method is proposed. Similar to this approach, after using the continuous-time chaotic oscillator alone, we have proposed a RNG design which uses a dual oscillator architecture with the proposed chaotic oscillator in order to increase the output throughput and the statistical quality of the generated bit sequences. In this design, the chaotic oscillator output signal is used to modulate the frequency of a slower clock. Then, with the rising edge (RE) of the chaos-modulated slower clock, fast clock is sampled. Finally, we have experimentally verified that the binary data obtained by this oscillator sampling technique pass the tests of full NIST random number test suite for a higher throughput speed than the one obtained by using chaotic oscillator alone. We expect that, this approach can tackle the external interference problem.

Section snippets

Proposed oscillator

The proposed chaotic oscillator is shown in Fig. 1. Assuming that the parasitic capacitances appearing between the collectors of the bipolar transistors and the ground are denoted by Cp, routine analysis of the circuit yields the following state equations: Cv1˙=-i3-(I0/β)tanh(v1/2VT),Li3˙=(v1-v2),Cpv2˙=i3-1R+1Rpv2+2RpVpsgn(sinΩt)+I0tanh(v1/2VT),where i3=iR-iL, β=Icollector/Ibase (current gain) and vp(t) is the external periodical pulse train defined as vp(t)=sgn(sinΩt) and VT is the thermal

Mechanism of chaos generation

It is known that Melnikov's conditions can be used to show the existence of horseshoes in nearly Hamiltonian forced planar dissipative systems. According to the Smale–Birkhoff Theorem [19], for a given planar perturbed nonlinear system of the form, x˙=f(x)+μg(x,t), where f and g are smooth functions and g is periodic in time with a period of Tγ, if the following conditions are satisfied:

  • 1.

    For μ=0, the system is Hamiltonian and has a homoclinic orbit passing through the saddle-type critical point.

  • 2.

Random bit generation

In [12], in order to obtain random binary data from an autonomous chaotic system, an interesting technique has been presented, which relies on generating a non-invertible binary data from the waveform of the given chaotic system. It should be noted that non-invertibility is a key feature for generating PRNGs [20].

To obtain binary random bits from the proposed chaotic attractor, we initially used the stroboscopic Poincaré map of the chaotic system of Eq. (2). A Poincaré section in the xy plane

Circuit simulations and experimental verification

In order to show the high-frequency operation capability of the proposed chaotic oscillator, the circuit in Fig. 1 has been simulated using SPICE with the model parameters of AMS SiGe 0.35μm BiCMOS process. The circuit was biased with ±1.5V power supply. The passive component values were: L=1μH, C=1pF, R=250Ω, Rp=120Ω and the biasing current was I0=1.8mA. The amplitude and frequency of the external square signal were 27mV and 43.7MHz, respectively. The observed phase-space corresponding to i3

Hardware realization of RNGs

We have initially generated random bits from the stroboscopic Poincaré map of the proposed chaotic oscillator. Then in order to increase the output throughput and the statistical quality of the generated bits, we have proposed a RNG design which uses a dual oscillator architecture with the proposed oscillator.

Conclusions

A novel continuous-time chaotic oscillator suitable for IC realization and two novel TRNGs based on this oscillator were presented. Numerical and experimental results presented in this paper not only verify the feasibility of the proposed circuit, but also encourage its use as the core of a high-performance IC TRNG as well. In conclusion, we have experimentally verified that when the frequency of the external periodical pulse signal is adjusted to 5.86 kHz the proposed TRNG, which mixes the

Salih Ergün received his B.Sc. and M.Sc. degrees in 1998 and 2000, respectively, in Electronics and Telecommunication Engineering from the İstanbul Technical University, İstanbul, Turkey, where he is currently working toward Ph.D. degree. In 2000, he joined the National Research Institute of Electronics & Cryptology, TÜBİTAK, Turkey, where he is currently with the Cryptographic Hardware group. His research interests are MOS IC design, chaotic oscillators, random number generators, with special

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    Salih Ergün received his B.Sc. and M.Sc. degrees in 1998 and 2000, respectively, in Electronics and Telecommunication Engineering from the İstanbul Technical University, İstanbul, Turkey, where he is currently working toward Ph.D. degree. In 2000, he joined the National Research Institute of Electronics & Cryptology, TÜBİTAK, Turkey, where he is currently with the Cryptographic Hardware group. His research interests are MOS IC design, chaotic oscillators, random number generators, with special emphasis on software and hardware for cryptographic applications.

    Serdar Özog˜uz received his B.Sc. degree in Electronics and Communication Engineering in 1991 and Ph.D. degree in Electronic Engineering in 2000 from the İstanbul Technical University, İstanbul, Turkey. Currently, he is a Assoc. Prof. with the Department of Electronics and Communication Engineering, İstanbul Technical University. His research interests include the design of analog circuits in particular nonlinear circuits.

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