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Low-power test pattern generator using modified LFSR

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Abstract

Low-power designs are getting increased significance in numerous applications like high-performance computing and wireless communication due to the rise in power dissipation. Power dissipation of VLSI (very large scale integration) circuits in test mode is much higher than in the normal operation mode due to the high frequency of applied test patterns. Product lifetime, yield, reduced performance, and circuit damage will result from this additional power consumption in testing. Therefore, the main objective of today’s test applications is to minimize power dissipation by increasing the correlation of applied successive test vectors. Low-power test pattern generator (TPG) using LFSR (linear feedback shift register) and binary to the excess-4 converter and binary ripple counter is proposed. The test vectors generated by the TPG have a high correlation between successive test vectors, which leads to minimum switching. During the testing of benchmark circuits, the proposed method shows a significant reduction in dynamic power consumption concerning its peer works.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Dr NGP Institute of Technology, Coimbatore, 641048, India

    V. Govindaraj

  2. Department of Electronics and Communication Engineering, Sri Eshwar College of Engineering, Coimbatore, 641202, India

    S. Dhanasekar

  3. Department of Electronics and Communication Engineering, Karunya Institute of Technology and Sciences, Coimbatore, 641114, India

    K. Martinsagayam

  4. Department of Technical Education, Uttar Pradesh, Kanpur, India

    Digvijay Pandey

  5. Department of Information Technology, College of Technology, Govind Ballabh Pant University of Agriculture and Technology Pantnagar, Udham Singh Nagar, Uttarakhand, India

    Binay Kumar Pandey

  6. Computer Science Engineering Department, Rajarambapu Institute of Technology, Rajaramnagar Sakharale, Tel Walwa Dist Sangli, Islampur, 415414, Maharashtra, India

    Vinay Kumar Nassa

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  1. V. Govindaraj
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  2. S. Dhanasekar
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  3. K. Martinsagayam
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  4. Digvijay Pandey
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  5. Binay Kumar Pandey
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  6. Vinay Kumar Nassa
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Correspondence to Digvijay Pandey.

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Govindaraj, V., Dhanasekar, S., Martinsagayam, K. et al. Low-power test pattern generator using modified LFSR. AS 7, 67–74 (2024). https://doi.org/10.1007/s42401-022-00191-5

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  • DOI: https://doi.org/10.1007/s42401-022-00191-5

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