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Network-on-Chip Trust Validation Using Security Assertions

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Abstract

Recent technological advancements enabled integration of a wide variety of Intellectual Property (IP) cores in a single chip, popularly known as System-on-a-Chip (SoC). Network-on-Chip (NoC) is a scalable solution that enables communication between a large number of IP cores in modern SoC designs. A typical SoC design methodology relies on third-party IPs to reduce cost and meet time-to-market constraints, leading to serious security concerns. NoC becomes an ideal target for attackers due to its distributed nature across the chip as well as its inherent ability in monitoring communications between the individual IP cores. This paper presents a comprehensive NoC trust validation framework using security assertions. It makes three important contributions. (1) We define a set of security vulnerabilities for NoC architectures, and propose security assertions to monitor these pre-silicon vulnerabilities. (2) In order to ensure that the generated assertions are valid, we utilize efficient test generation techniques to activate these security assertions. (3) We develop on-chip triggers based on synthesized security assertions as well as efficient security-aware signal selection techniques for effective post-silicon debug. Experimental results show that our proposed framework is scalable and effective in capturing security vulnerabilities as well as functional bugs with minor hardware overhead.

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Notes

  1. Most NoC architectures facilitate flits, which is a further breakdown of a packet used for flow control purposes. We stick to the level of packets for the ease of explanation as our method remains the same at the flit level as well.

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Authors and Affiliations

  1. University of Florida, Gainesville, USA

    Aruna Jayasena, Hasini Witharana & Prabhat Mishra

  2. Indian Institute of Technology, Jodhpur, India

    Binod Kumar

  3. University of Moratuwa, Moratuwa, Sri Lanka

    Subodha Charles

Authors
  1. Aruna Jayasena
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  2. Binod Kumar
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  3. Subodha Charles
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  4. Hasini Witharana
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  5. Prabhat Mishra
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Corresponding author

Correspondence to Aruna Jayasena.

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Funding

This work was partially supported by grants from National Science Foundation (CCF-1908131) and Semiconductor Research Corporation (2020-CT-2934).

Competing Interests

The authors have no relevant financial or non-financial interests to disclose.

Author Contributions

All authors contributed to the study conception and design. Manuscript preparation, experimental setup, and analysis were performed by Aruna Jayasena and Binod Kumar. The assertion validation part was performed by Hasini Witharana. The first draft of the manuscript was written by Subodha Charles and Prabhat Mishra and all authors commented on previous versions of the manuscript. All authors read and approved the final manuscript.

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All the data and the analysis results that were generated during the experiments are available in the manuscript.

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Jayasena, A., Kumar, B., Charles, S. et al. Network-on-Chip Trust Validation Using Security Assertions. J Hardw Syst Secur 6, 79–94 (2022). https://doi.org/10.1007/s41635-022-00129-5

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