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Large-Area Automated Layout Extraction Methodology for Full-IC Reverse Engineering

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Abstract

A high degree of automation is required when facing full-IC reverse engineering. In this paper, we present a methodology to delayer the chip, acquire SEM images of each layer, obtain the three-dimensional layer reconstruction, and generate a vectorized file in GDSII format for further automatic netlist extraction. A custom software tool named GDS-X has been developed to perform all the required steps from image acquisition to the GDSII file generation. Applying a novel tile mosaicking strategy and using state-of-the-art machine learning techniques for image segmentation, this software reduces dramatically the time required to complete these procedures while minimizing errors compared to old manual reverse engineering techniques.

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Acknowledgements

The authors would like to thank the IMB-CNM clean room staff and specially the RIE, SEM image acquisition and carbon deposition teams for their valuable support and advice.

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Correspondence to Jofre Pallares.

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This work has been partially funded by D+T Microelectronica A.I.E.

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Quijada, R., Dura, R., Pallares, J. et al. Large-Area Automated Layout Extraction Methodology for Full-IC Reverse Engineering. J Hardw Syst Secur 2, 322–332 (2018). https://doi.org/10.1007/s41635-018-0051-4

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  • DOI: https://doi.org/10.1007/s41635-018-0051-4

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