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High Speed High Resolution Current Comparator and its Application to Analog to Digital Converter

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Abstract

This paper introduces a high speed high resolution current comparator which includes the current differencing stage and employs non linear feedback in the gain stage. The usefulness of the proposed comparator is demonstrated by implementing a 3-bit current mode flash analog-to-digital converter (ADC). Simulation program with integrated circuit emphasis (SPICE) simulations have been carried out to verify theoretical proposition and performance parameters of both comparator and ADC are obtained using TSMC 0.18 µm CMOS technology parameters. The current comparator shows a resolution of ±5 nA and a delay of 0.86 ns for current difference of ±1 µA. The impact of process variation on proposed comparator propagation delay has been studied through Monte Carlo simulation and it is found that percentage change in propagation delay in best case is 1.3 % only and in worst case is 9 % only. The ADC exhibits an offset, gain error, differential nonlinearity (DNL) and integral nonlinearity (INL) of 0.102 µA, 0.99, −0.34 LSB and 0.0267 LSB, respectively. The impact of process variation on ADC has also been studied at different process corners.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Delhi Technological University, Delhi, 110042, India

    Ranjana Sridhar, Neeta Pandey & Asok Bhattacharyya

  2. Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University for Women, Delhi, 110006, India

    Veepsa Bhatia

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  1. Ranjana Sridhar
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  2. Neeta Pandey
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  3. Asok Bhattacharyya
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  4. Veepsa Bhatia
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Correspondence to Veepsa Bhatia.

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Sridhar, R., Pandey, N., Bhattacharyya, A. et al. High Speed High Resolution Current Comparator and its Application to Analog to Digital Converter. J. Inst. Eng. India Ser. B 97, 147–154 (2016). https://doi.org/10.1007/s40031-015-0189-1

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  • DOI: https://doi.org/10.1007/s40031-015-0189-1

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