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An Efficient Implementation of Divergence State Estimation with Biogeography-Based Optimization (DSEBBO) Framework in FPGA-Based Multiprocessor System

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Abstract

In recent years, Field Programmable Gate Array (FPGA) has different, and novel combinations of soft and hard cores embedded with accelerators in the same chip. At present, “Heterogeneous Multiprocessor System-on-Chip” technology meets the needs of the FPGA architecture as it not only consumes less space but also its design is implemented to enhance the performance resulting in decreased power consumption. However, traditional approaches can work within a limited range of values incurring high-power consumption, and they need substantial hardware resources involving complex procedures. In our proposed work, the combination of Graph Theory Estimator and Divergence State Estimation with Biogeography-Based Optimization (DSEBBO) is introduced. The principle notion of this proposed scheme is to optimize the required area resources and power consumption of the overall architecture by exploring the design space in a minimal time. The architecture uses a less number of hardware resources with a better outcome. The performances such as the latency, power consumption, delay, area and data rate are achieved better than the traditional works, and it is also application-aware with a multitask system. While comparing the outcome with the conventional asymmetric heterogeneous MPSoC method, the new DSEBBO design exhibits the performance improvement of 26.87% in data rate, and 37.18% reduction in average power consumption and 63.61% reduction in delay analysis under various traffic scenarios.

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References

  1. Othman, S.B.; Salem, A.K.B.; Saoud, S.B.: MPSoC design of RT control applications based on FPGA soft core processors. In: Electronics, Circuits, and Systems, ICECS, pp. 404–409. IEEE (2008)

  2. Vincent, V.; Avasare, P.; Eeckhaut, H.; Verkest, D.; Corporaal, H.: Run-time management of a MPSoC containing FPGA fabric tiles. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 16(1), 24–33 (2008)

    Article  Google Scholar 

  3. Lukovic, S.; Fiorin, L.: An automated design flow for NoC-based MPSoCs on FPGA. In: The 19th IEEE/IFIP International Symposium on Rapid System Prototyping, RSP’08, pp. 58–64. IEEE (2008)

  4. Xilinx, Zynq-7000: All Programmable SoC Technical Reference Manual (2018). http://www.xilinx.com/support/documentation/userguides/ug-585-Zynq-7000-TRM.pdf. Accessed 21 Aug 2019

  5. Altera, Cyclone V. FPGAs (2012). https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/po/ss-cyclone-v-fpgas.pdf. Accessed 21 Aug 2019

  6. SmartFusion®2SoC FPGAs (2017). https://www.microsemi.com/…/131308-smartfusion2-product-information-brochure. Accessed 21 Aug 2019

  7. Xilinx. Virtex ultra-scale (2014). http://www.xilinx.com/products/silicondevices/fpga/virtex-ultrascale.html. Accessed 21 Aug 2019

  8. Martin, G.: Overview of the MPSoC design challenge. In: 43rd ACM/IEEE Design Automation Conference (2006)

  9. Fedorova, A.; Saez, J.C.; Shelepov, D.; Prieto, M.: Maximizing power efficiency with asymmetric multicore systems. Commun. ACM 52(12), 48–57 (2009)

    Article  Google Scholar 

  10. Jozwiak, L.; Lindwer, M.: Issues and challenges in development of massively-parallel heterogeneous MPSoCs based on adaptable ASIPs. In: 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing, pp. 483–487, IEEE (2011)

  11. Jozwiak, L.: Heterogeneous MPSoC technology for modern cyber—physical systems. Inform. MIDEM J. Microelectron. Electron. Compon. Mater. 44(4), 264–279 (2014)

    Google Scholar 

  12. Bouthaina, D.; Baklouti, M.; Niar, S.; Abid. M.: Shared hardware accelerator architectures for heterogeneous MPSoCs. In: 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), IEEE (2013)

  13. Carvalho, E.; Moraes, F.: Congestion-aware task mapping in heterogeneous MPSoCs. In: 2008 International Symposium on System-on-Chip. IEEE (2008)

  14. Li, K.; Tang, X.; Li, K.: Energy-efficient stochastic task scheduling on heterogeneous computing systems. IEEE Trans. Parallel Distrib. Syst. 25(11), 2867–2876 (2014)

    Article  Google Scholar 

  15. Duran, A.; Ayguade, E.; Badia, R.M.; Labarta, J.; Martinell, L.; Maturely, X.; Planas, J.: Ompss: a proposal for programming heterogeneous multi-core architectures. Parallel Process. Lett. 21(2), 173–193 (2011)

    Article  MathSciNet  Google Scholar 

  16. Augonnet, C.; Thibault, S.; Namyst, R.; Wacrenier, P.A.: StarPU: a unified platform for task scheduling on heterogeneous multicore architectures. Concurr. Comput. Pract. Exp. 23(2), 187–198 (2011)

    Article  Google Scholar 

  17. Hakem, M.; Butelle, F.: Dynamic critical path scheduling parallel programs onto multiprocessors. In: 19th IEEE International Parallel and Distributed Processing Symposium, (IPDPS’05). IEEE (2005)

  18. Topcuoglu, H.; Hariri, S.; Wu, M.Y.: Performance-effective and low-complexity task scheduling for heterogeneous computing. IEEE Trans. Parallel Distrib. Syst. 13(3), 260–274 (2002)

    Article  Google Scholar 

  19. Blank, T.: A survey of hardware accelerators used in computer-aided design. IEEE Des. Test Comput. 1(3), 21–39 (1984)

    Article  Google Scholar 

  20. Howard, N.J.; Tyrrell, A.M.; Allinson, N.M.: The use of field-programmable gate arrays for the hardware acceleration of design automation tasks. VLSI Des. 4(2), 135–139 (1996)

    Article  Google Scholar 

  21. Safaei, A.; Wu, Q.M.J.; Yang, Y.: System-on-a-chip (SoC)-based hardware acceleration for foreground and background identification. J. Frankl. Inst. Elsevier 355(4), 1888–1912 (2018)

    Article  Google Scholar 

  22. Diaz, L.; Gonzalez, E.; Villar, E.; Sanchez, P.: VIPPE, parallel simulation and performance analysis of multi-core embedded systems on multi-core platforms. In Design of Circuits and Integrated Systems. IEEE (2014)

  23. Amaricai, A.; Dobre, A.; Boncalo, O.; Tanase, A.; Valuch, C.: Models and implementations of hardware interface modules in a multi-processor system-on-chip simulator. In: 6th IEEE International Symposium on Applied Computational Intelligence and Informatics, (SACI), pp. 433–437. IEEE (2011)

  24. Pimentel, A.D.; Stralen, P.V.: Scenario-based design space exploration. In: Ha, S., Teich, J. (eds.) Handbook of Hardware/Software Codesign. Springer, Dordrecht (2017)

    Google Scholar 

  25. Shah, S.A.A.; Farkas, B.; Meyer, R.; Berekovic, M.: Accelerating MPSoC design space exploration within system-level frameworks. In: 2016 IEEE Nordic Circuits and Systems Conference (NORCAS). IEEE (2016)

  26. Yudi, J.; Llanos, C.H.; Huebner, M.: System-level design space identification for many-core vision processors. Microprocess. Microsyst. 52, 2–22 (2017)

    Article  Google Scholar 

  27. Makni, M.; Niar, S.; Baklouti, M.; Abid, M.: HAPE: a high-level area-power estimation framework for FPGA-based accelerators. Microprocess. Microsyst. 63, 11–27 (2018)

    Article  Google Scholar 

  28. Ouni, B.; Mhedbi, I.; Trabelsi, C.; Atitallah, R.B.; Belleudy, C.: Multi-level energy/power-aware design methodology for MPSoC. J. Parallel Distrib. Comput. 100, 203–215 (2017)

    Article  Google Scholar 

  29. Qadri, M.Y.; Qadri, N.N.; Maier, K.D.: Fuzzy logic based energy and throughput aware design space exploration for MPSoCs. Microprocess. Microsyst. 40, 113–123 (2016)

    Article  Google Scholar 

  30. Rosvall, K.; Khalilzad, N.; Ungureanu, G.; Sander, I.: Throughput propagation in constraint-based design space exploration for mixed-criticality systems. In: RAPIDO ‘17: Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools. vol. 4, pp. 1–8 (2017)

  31. Xu, S.; Liu, S.; Liu, Y.; Mahapatra, A.; Villaverde, M.; Moreno, F.; Schafer, B.C.: Design space exploration of heterogeneous MPSoCs with variable number of hardware accelerators. Microprocess. Microsyst. 65, 169–179 (2019)

    Article  Google Scholar 

  32. Murtza, S.A.; Ahmad, A.; Qadri, M.Y.; et al.: Optimizing energy and throughput for MPSoCs: an integer particle swarm optimization approach. Computing 100, 227–244 (2018)

    Article  MathSciNet  Google Scholar 

  33. Quan, W.: Scenario-Based Run-Time Adaptive Multi-Processor System-on-Chip. Ph.D. dissertation (2015)

  34. Wolf, W.; Jerraya, A.A.; Martin, G.: Multiprocessor system-on-chip (MPSoC) technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(10), 1701–1713 (2008)

    Article  Google Scholar 

  35. Ma, H.; Simon, D.; Siarry, P.; Yang, Z.; Fei, M.: Biogeography-based optimization: a 10-year review. IEEE Trans. Emerg. Top. Comput. Intell. 1(5), 391–407 (2017)

    Article  Google Scholar 

  36. Chen, L.; Mitra, T.: Shared reconfigurable fabric for multi-core customization. In: 48th ACM/EDAC/IEEE Design Automation Conference (DAC) (2011)

  37. Dammak, B.; Baklouti, M.; Benmansour, R.; Niar, S.; Abid, M.: Hardware resource utilization optimization in FPGA-based heterogeneous MPSoC architectures. Microprocess. Microsyst. 39(8), 1108–1118 (2015)

    Article  Google Scholar 

  38. Sakthivel, E.; Malathi, V.; Arunraja, M.: MATHA: multiple sense amplifiers with a transceiver for high-performance improvement in NoC Architecture. Microprocess. Microsyst. 38(7), 692–706 (2014)

    Article  Google Scholar 

  39. Zheng, Y.; Lu, X.; Zhang, M.; Chen, S.: Biogeography-Based Optimization: Algorithms and Applications. Springer, Beijing (2019)

    Book  Google Scholar 

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Acknowledgements

The authors would like to thank the faculty members of the Department of Electronics and Communication Engineering at Anna University Regional Campus Madurai for their immense support and motivation.

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This research did not receive any specific grant from funding agencies in the public, commercial, or not-for-profit sectors.

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Correspondence to Isaivani Mariyappan.

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Mariyappan, I., Veluchamy, M. & Ramachandradurai, S. An Efficient Implementation of Divergence State Estimation with Biogeography-Based Optimization (DSEBBO) Framework in FPGA-Based Multiprocessor System. Arab J Sci Eng 45, 6649–6660 (2020). https://doi.org/10.1007/s13369-020-04634-z

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