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System-on-programmable-chip implementation of diminishing learning based pattern recognition system

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Abstract

Support vector machine (SVM) is one of the state-of-the-art tools for linear and nonlinear pattern classification. One of the design issues in SVM classifier is reducing the number of support vectors without compromising the classification accuracy. A technique denoted as diminishing learning (DL) is already proposed in literature for an SVM based multi-class isolated digit recognition system using speaker dependent TI46 database of isolated digits. In this paper, the computational complexity for SVM and SVM-DL based isolated digit recognition system is studied and the computation time for both the classifiers is evaluated by system-on-programmable-chip (SOPC) implementation of the recognition system onto an Altera Cyclone II Series FPGA using Nios II Soft-core processor. The number of support vectors is reduced by 38.28–90.25 % on using SVM-DL for isolated digit recognition problem. This in turn reduces the classification time for SVM-DL by 31.45–91.78 % over SVM. Recognition accuracies of 97 and 98 % are achieved for SVM classifier with and without DL technique, respectively. The study confirms the effect of, the order in which the classes are classified, on the recognition accuracy. For the TI46 database, about 2–4 % increase in recognition accuracy is obtained by choosing the optimum order for SVM-DL classifier. The proposed SOPC implementation of SVM-DL based recognition system can be employed for various other pattern recognition applications too such as face recognition, character recognition and target recognition.

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Acknowledgments

The authors would like to thank all the anonymous reviewers for their constructive comments on an earlier version of this paper.

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Authors and Affiliations

  1. Department of ECE, National Institute of Technology, NITT, Trichy, TN, 620015, India

    B. Venkataramani

  2. Crucible of Research and Innovation (CORI), PES Institute of Technology, PESIT, Bangalore, KA, 560085, India

    J. Manikandan

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  1. J. Manikandan
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  2. B. Venkataramani
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Correspondence to J. Manikandan.

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Manikandan, J., Venkataramani, B. System-on-programmable-chip implementation of diminishing learning based pattern recognition system. Int. J. Mach. Learn. & Cyber. 4, 347–363 (2013). https://doi.org/10.1007/s13042-012-0102-z

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  • DOI: https://doi.org/10.1007/s13042-012-0102-z

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