Skip to main content
SpringerLink
Log in

Impact of Interface Trap Distribution on the Performance of LTPS TFT

  • Research
  • Published:
Silicon Aims and scope Submit manuscript

Abstract

This article presents a multiple trapping and release model (MTR) based technology computer-aided design (TCAD) investigation of low-temperature poly-silicon (LTPS) thin film transistors (TFTs). To consider the role of localized and delocalized states in carrier transport, the proposed simulation framework considers the inclusion of interface traps in the TFTs, which effectively represent the defects present in the poly-Si/ gate dielectric interface and the grain boundaries (GBs). The device performance is reported for Gaussian and double-exponential deep and tail state trap distribution of acceptor-like and donor-like interface traps by varying the trap-distribution parameters such as peak trap concentration (N0) and location of peak (Emid). Electrical parameters such as on and off-state currents, threshold voltage and subthreshold swing are reported for the parametric investigation. As the trap distribution penetrates deeper into the bandgap from the band edges, the performance deteriorates, as evident from the increase in subthreshold swing and threshold voltage. The impact and results of the analyses infer that the proposed framework can be applied to predict and model LTPS TFTs through a design-and-simulation approach as proposed in the article.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

Data Availability

Not applicable.

References

  1. Zhao S, Meng Z, Zhou W et al (2013) Bridged-grain polycrystalline silicon thin-film transistors. IEEE Trans Electron Devices 60:1965–1970

    Article  CAS  Google Scholar 

  2. Kito K, Kitajima S, Matsuda T et al (2019) Infrared sensors using poly-Si thin-film transistors for proximity sensors integrated in smartphone displays. J Soc Inf Disp 27:147–154

    Article  CAS  Google Scholar 

  3. Saburova VI, Kamaev GN, Cherkaev AS, Gridchin VA (2018) Modeling of the temperature dependence of polycrystalline-Si conductivity in TCAD Sentaurus environment. In: 2018 XIV International Scientific-Technical Conference on Actual Problems of Electronics Instrument Engineering (APEIE). IEEE, pp 109–112

  4. Li J, Bansal A, Roy K (2007) Poly-Si thin-film transistors: An efficient and low-cost option for digital operation. IEEE Trans Electron Devices 54:2918–2929

    Article  CAS  Google Scholar 

  5. Zaidi B, Hadjoudja B, Chouial B et al (2015) Effect of Secondary Annealing on the Electrical Properties of Polysilicon Thin Films. Silicon 7:293–295

    Article  CAS  Google Scholar 

  6. Dimitriadis CA, Tassis DH, Economou NA, Lowe AJ (2001) Determination of bulk states and interface states distributions in polycrystalline silicon thinfilm transistors Determination of bulk states and interface states distributions in polycrystalline silicon thin-film transistors. 2919. https://doi.org/10.1063/1.354648

  7. Jacunski MD, Shur MS, Hack M (1996) Threshold voltage, field effect mobility, and gate-to-channel capacitance in polysilicon TFT’s. IEEE Trans Electron Devices 43:14331440

    Article  Google Scholar 

  8. Miyano S, Shimizu Y, Murakami T, Miura-Mattausch M (2008) A surface potential based poly-Si TFT model for circuit simulation. In: 2008 International Conference on Simulation of Semiconductor Processes and Devices. IEEE, pp 373–376

  9. Torricelli F, Meijboom JR, Smits E et al (2011) Transport physics and device modeling of zinc oxide thin-film transistors part I: Long-channel devices. IEEE Trans Electron Devices 58:2610–2619

    Article  CAS  Google Scholar 

  10. Baccarani G, Spadini G (2012) Transport properties of polycrystalline silicon films. 5565. https://doi.org/10.1063/1.324477

  11. Werner J, Peisl M (1985) Exponential band tails in polycrystalline semiconductor films. Phys Rev B 31:6881–6883. https://doi.org/10.1103/PhysRevB.31.6881

    Article  CAS  Google Scholar 

  12. Lee S-C, Lee MJ (2000) Effects of multi-energetic grain-boundary trapping states on the electrical characteristics of poly-CdSe thin film transistors. J Appl Phys 88:1999–2004

    Article  CAS  Google Scholar 

  13. Guerrieri R, Ciampolini P, Gnudi A et al (1986) Numerical simulation of polycrystalline-silicon MOSFET’s. IEEE Trans Electron Devices 33:1201–1206

    Article  Google Scholar 

  14. Armstrong GA, Uppal S, Brotherton SD, Ayres JR (1997) Modeling of laser-annealed polysilicon TFT characteristics. IEEE Electron Device Lett 18:315–318

    Article  CAS  Google Scholar 

  15. King T, Hack MG, Wu I (1994) Effective density-of-states distributions for accurate modeling of polycrystalline-silicon thin-film transistors. J Appl Phys 75:908–913

    Article  CAS  Google Scholar 

  16. Hossain FM, Nishii J, Takagi S et al (2004) Modeling of grain boundary barrier modulation in ZnO invisible thin film transistors. Phys E Low-dimensional Syst Nanostructures 21:911–915

    Article  CAS  Google Scholar 

  17. Lee S, Nathan A (2016) Conduction threshold in accumulation-mode InGaZnO thin film transistors. Sci Rep 6:22567

    Article  CAS  PubMed  PubMed Central  Google Scholar 

  18. Hossain FM et al (2003) Modeling and simulation of polycrystalline ZnO thin-film transistors. J Appl Phys 94(12):7768–7777

    Article  CAS  Google Scholar 

  19. Asanovski R, Selmi L, Palestri P, Caruso E (2020) 1/f noise model based on trap-assisted tunneling for ultra-thin oxides MOSFETs. TechRxiv. https://doi.org/10.36227/techrxiv.12579641.v1

  20. Seto JYW (1975) The electrical properties of polycrystalline silicon films. J Appl Phys 46:5247–5254. https://doi.org/10.1063/1.321593

    Article  CAS  Google Scholar 

  21. Dobrescu L, Petrov M, Dobrescu D, Ravariu C (2000) Threshold voltage extraction methods for MOS transistors. In: 2000 International Semiconductor Conference. 23rd Edition. CAS 2000 Proceedings (Cat. No. 00TH8486). IEEE, pp 371–374

  22. Ortiz-Conde A, Sánchez FJG, Liou JJ et al (2002) A review of recent MOSFET threshold voltage extraction methods. Microelectron Reliab 42:583–596

    Article  Google Scholar 

  23. Ortiz-Conde A, García-Sánchez FJ, Muci J et al (2013) Revisiting MOSFET threshold voltage extraction methods. Microelectron Reliab 53:90–104

    Article  Google Scholar 

  24. Kandpal K, Gupta N, Singh J, Shekhar C (2020) On the Threshold Voltage and Performance of ZnO-Based Thin-Film Transistors with a ZrO2 Gate Dielectric. J Electron Mater 49(5):3156–3164. https://doi.org/10.1007/s11664-020-08055-4

  25. Desai MS, Kandpal K, Goswami R (2021) A Multiple-Trapping-and-Release Transport Based Threshold Voltage Model for Oxide Thin Film Transistors. J Electron Mater 50:4050–4057. https://doi.org/10.1007/s11664-021-08907-7

    Article  CAS  Google Scholar 

Download references

Acknowledgements

The Authors would like to acknowledge the software support by IIIT Allahabad, SEED GRANT NO. IIITA/RO/323/2021.

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Indian Institute of Information Technology Allahabad Prayagraj, Prayagraj, U.P., India

    Saurabh Jaiswal, Manish Goswami & Kavindra Kandpal

  2. Department of ECE, Tezpur University, Assam, India

    Rupam Goswami

Authors
  1. Saurabh Jaiswal
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Rupam Goswami
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Manish Goswami
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Kavindra Kandpal
    View author publications

    You can also search for this author in PubMed Google Scholar

Contributions

All authors contributed to the study's conception and design. TCAD simulations were performed by Saurabh Jaiswal. The first draft was written by Saurabh Jaiswal, Kavindra Kandpal, and Rupam Goswami. Theoretical and conceptual analysis was done by Saurabh Jaiswal and Kavindra Kandpal. Kavindra Kandpal and Manish Goswami supervised the work. All authors read and approved the final manuscript.

Corresponding author

Correspondence to Kavindra Kandpal.

Ethics declarations

Ethics approval

Not applicable.

Consent to Participate and Consent for Publication

Not applicable.

Competing Interests

None.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Jaiswal, S., Goswami, R., Goswami, M. et al. Impact of Interface Trap Distribution on the Performance of LTPS TFT. Silicon 15, 6269–6281 (2023). https://doi.org/10.1007/s12633-023-02503-6

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s12633-023-02503-6

Keywords

Search

Navigation