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Gate Engineered Silicon Nanowire FET with Coaxial Inner Gate for Enhanced Performance

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Abstract

In this work, we have proposed and analysed the Triple Material Dual Gate Cylindrical Nanowire (TMDG CNW) device structure at the 10 nm technology node for improved device performance over conventional nanowire. The proposed structure was validated using the Sentaurus TCAD tool. By incorporating three materials with different work functions as gate electrodes, using a dielectric stack and halo doping in the channel region, the device performance has been enhanced and immunity to short channel effects (SCE) has been improved further. An additional gate-coaxial inner gate other than the outer gate has been added to the TMDG CNW structure, which further improves the device performance. The proposed device has higher drain current, good immunity to SCE and process variations, better gate control over the channel, and overall better device performance. This gate/channel engineered nanowire FET with an additional coaxial inner gate has been reported for the first time.

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Acknowledgements

Authors are thankful to Electronics and Communication Department, JIIT for providing Sentaurus TCAD Tool for simulation work.

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Authors and Affiliations

  1. Department of Electronics & Communication Engineering, Jaypee Institute of Information Technology, Noida, India

    Mandeep Singh Narula & Archana Pandey

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  1. Mandeep Singh Narula
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  2. Archana Pandey
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Work has been done by Mr. Mandeep Singh Narula under the supervision of Dr. Archana Pandey.

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Correspondence to Mandeep Singh Narula.

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Narula, M.S., Pandey, A. Gate Engineered Silicon Nanowire FET with Coaxial Inner Gate for Enhanced Performance. Silicon 15, 4217–4227 (2023). https://doi.org/10.1007/s12633-023-02340-7

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