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Temperature Influence on Dielectric Tunnel FET Characterization and Subthreshold Characterization

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Abstract

VLSI technology is being developed to lower the size of semiconductor devices due to the increasing importance of integrated circuits (ICs). Short channel effects, for example, make it difficult to operate these devices as technology continues to advance. Thus, the device’s downsizing is made possible by designing new structures and leveraging new methods of current transfer. Many researchers believe that for low-power applications, TFETs, which rely on band-to-band tunnelling for current transfer, are a viable alternative to MOSFETs. For the purposes of mixed signal applications, this study examines the TFET from the perspective of both device and circuit-level simulations. It has been suggested that the negative capacitance (NC) of ferroelectrics could be used to overcome the basic limit of MOSFETs by utilising the differential amplification of the gate voltage under certain circumstances. It’s a negative capacitance heterostructure based on these two ideas. As a result, the surrounding gate structure concept has improved the output characteristics of TFETs. By reducing channel resistance and tunnelling width, the suggested device size can be optimised. The TFET topologies discussed above are ideal for low-power switching and analogue RF applications. The proposed analytical models were tested using MATLAB and confirmed using the nanoscale device simulator Technology Computer-Aided Design (TCAD). The stacked surrounding gate TFET device, according to the data, is an interesting device contender to replace VLSI technology.

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Acknowledgements

The authors are thankful to Gokaraju Rangaraju Institute of Engineering & Technology, Hyderabad for their cooperation and support during this research work.

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Authors and Affiliations

  1. Department of ECE, MVJ College of Engineering, Bangalore, Karnataka, 560067, India

    S. Kanithan

  2. Department of Information Science and Engineering, MVJ College of Engineering, Bangalore, Karnataka, 560067, India

    S. Anthoniraj

  3. Department of Robotics and Automation Engineering, Muthayammal College of Engineering, Kakkaveri, Rasipuram, Tamil Nadu, 637408, India

    P. Manikandan

  4. Department of ECE, Sreenidhi Institute of Science and Technology, Hyderabad, Telangana, 501301, India

    T. Ramaswamy

  5. Department of ECE, Jaypee University of Engineering and Technology, Guna, 473226, India

    Ravi Kumar

  6. Department of ECE, Gokaraju Rangaraju Institute of Engineering and Technology, Hyderabad, Telangana, 500090, India

    N. Arun Vignesh & Asisa Kumar Panigrahy

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  1. S. Kanithan
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  2. S. Anthoniraj
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  6. N. Arun Vignesh
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  7. Asisa Kumar Panigrahy
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Contributions

N Arun Vignesh, and Asisa Kumar Panigrahy: Conceptualization; S Kanithan, N Arun Vignesh, and Asisa Kumar Panigrahy: investigation; S Kanithan, S Anthoniraj, T Ramaswamy, Ravi Kumar, N Arun Vignesh, and Asisa Kumar Panigrahy: resources; S Kanithan, S Anthoniraj, T Ramaswamy, and Ravi Kumar: data curation; N. Arun Vignesh, S Kanithan and Asisa Kumar Panigrahy: writing—original draft preparation; N. Arun Vignesh, S Kanithan and Asisa Kumar Panigrahy: writing—review and editing; N. Arun Vignesh, S Kanithan and Asisa Kumar Panigrahy: visualization; N Arun Vignesh, and Asisa Kumar Panigrahy: supervision.

Corresponding author

Correspondence to N. Arun Vignesh.

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Kanithan, S., Anthoniraj, S., Manikandan, P. et al. Temperature Influence on Dielectric Tunnel FET Characterization and Subthreshold Characterization. Silicon 14, 11483–11491 (2022). https://doi.org/10.1007/s12633-022-01776-7

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  • DOI: https://doi.org/10.1007/s12633-022-01776-7

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