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Design Optimization of Nanotube Tunnel Field-Effect Transistor with Bias-Induced Electron-Hole Bilayer

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Abstract

In this paper, a novel nanotube tunneling field-effect transistor (NT-TFET) with bias-induced electron-hole bilayer (EHBNT-TFET) is proposed for the first time. By the intentional misalignment and an asymmetric bias configuration of the inner-gate and outer-gate, the line tunneling takes place inside the channel, significantly improving the tunneling rate and area. The device principle and performance are investigated by calibrated 3-D TCAD simulations. Compared to the conventional NT-TFET, the proposed EHBNT-TFET exhibits an increased ON-state current (ION) about 57.2 times and a sub-60 mV/dec subthreshold swing for seven orders of magnitude of drain current. Furthermore, the increased ION and reduced gate capacitance achieve improved dynamic performance. Compared with conventional NT-TFET, the intrinsic delay decreased about 142 times is obtained in EHBNT-TFET.

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The data and material that support the findings of this study are available on request from the corresponding author.

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References

  1. Taur Y (2002) CMOS design near the limit of scaling. IBM J Res Dev 46:213–222

    Article  Google Scholar 

  2. Ionescu AM, Michielis LD, Dagtekin N, et al (2011) Ultra low power: emerging devices and their benefits for integrated circuits. Tech Dig - Int Electron Devices Meet IEDM 378–381

  3. Choi WY, Park BG, Lee JD, Liu TJK (2007) Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett 28:743–745

  4. Ionescu AM, Riel H (2011) Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479:329–337

    Article  CAS  Google Scholar 

  5. Khan AI, Yeung CW, Hu C, Salahuddin S (2011) Ferroelectric negative capacitance MOSFET: capacitance tuning & antiferroelectric operation. Tech Dig - Int Electron Devices Meet IEDM 255–258

  6. Gopalakrishnan K, Griffin PB, Plummer JD (2005) Impact ionization MOS (I-MOS)-part I : device and circuit simulations. IEEE Trans Electron Devices 52:69–76

    Article  CAS  Google Scholar 

  7. Theis TN, Solomon PM (2010) It’s time to reinvent the transistor ! Science 1600–1601

  8. Raushan MA, Alam N, Siddiqui MJ (2018) Dopingless tunnel field-effect transistor with oversized Back gate: proposal and investigation. IEEE Trans Electron Devices 65:4701–4708

    Article  CAS  Google Scholar 

  9. Kumar MJ, Janardhanan S (2013) Doping-less tunnel field effect transistor: design and investigation. IEEE Trans Electron Devices 60:3285–3290

  10. Raad BR, Tirkey S, Sharma D, Kondekar P (2017) A new design approach of Dopingless tunnel FET for enhancement of device characteristics. IEEE Trans Electron Devices 64:1830–1836

    Article  CAS  Google Scholar 

  11. Hanna AN, Fahad HM, Hussain MM (2015) InAs/Si hetero-junction nanotube tunnel transistors. Sci Rep 5:9843–9849

    Article  CAS  Google Scholar 

  12. Kim SH, Agarwal S, Jacobson ZA et al (2010) Tunnel field effect transistor with raised germanium source. IEEE Electron Device Lett 31:1107–1109

    Article  CAS  Google Scholar 

  13. Boucart K, Ionescu AM (2007) Double-gate tunnel FET with high-κ gate dielectric. IEEE Trans Electron Devices 54:1725–1733

    Article  CAS  Google Scholar 

  14. Bhuwalka KK, Schulze J, Eisele I (2004) Performance enhancement of vertical tunnel field-effect transistor with SiGe in the δp+ layer. Japanese J Appl Physics 43:4073–4078

    Article  CAS  Google Scholar 

  15. Abdi DB, Kumar MJ (2014) In-built N+ pocket p-n-p-n tunnel field-effect transistor. IEEE Electron Device Lett 35:1170–1172

    Article  CAS  Google Scholar 

  16. Seo JH, Yoon YJ, Lee S et al (2015) Design and analysis of Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET). Curr Appl Phys 15:208–212

    Article  Google Scholar 

  17. Lattanzio L, Michielis LD, Ionescu AM (2012) The electron-hole bilayer tunnel FET. Solid State Electron 74:85–90

  18. Lattanzio L, Michielis LD, Ionescu AM (2012) Complementary Germanium Electron–Hole Bilayer Tunnel FET for Sub-0.5-V Operation. IEEE Electron Device Lett 33:167–169

  19. Padilla JL, Alper C, Godoy A et al (2015) Impact of asymmetric configurations on the Heterogate germanium Electron-hole bilayer tunnel FET including quantum confinement. IEEE Trans Electron Devices 62:3560–3566

    Article  CAS  Google Scholar 

  20. Kim S, Choi WY, Park BG (2018) Vertical-structured electron-hole bilayer tunnel field-effect transistor for extremely low-power operation with high scalability. IEEE Trans Electron Devices 65:2010–2015

    Article  CAS  Google Scholar 

  21. Fahad HM, Smith CE, Rojas JP, Hussain MM (2011) Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits. Nano Lett 11:4393–4399

    Article  CAS  Google Scholar 

  22. Hanna AN, Hussain MM (2015) Si/Ge hetero-structure nanotube tunnel field effect transistor. J Appl Phys 117:014310

    Article  Google Scholar 

  23. Apoorva, Kumar N, Amin Si, Anad S et al (2020) Design and Performance Optimization of Novel Core–Shell Dopingless GAA-Nanotube TFET With Si0.5Ge0.5-Based Source. IEEE Trans Electron Devices 67:789–795

  24. Fahad HM, Hussain MM (2013) High-performance silicon nanotube tunneling FET for ultralow-power logic applications. IEEE Trans Electron Devices 60:1034–1039

    Article  CAS  Google Scholar 

  25. Tekleab D, Tran H H, Sleight J W, Chidambarrao D (2012) silicon nanotube mosfet. US Patent 0217468, Aug. 30, 2012.

  26. Musalgaonkar G, Sahay S, Saxena RS, Kumar MJ (2019) A line tunneling field-effect transistor based on misaligned core-shell gate architecture in emerging nanotube fets. IEEE Trans Electron Devices 66:2809–2816

    Article  CAS  Google Scholar 

  27. Musalgaonkar G, Sahay S, Saxena RS, Kumar MJ (2019) Nanotube tunneling FET with a Core source for Ultrasteep subthreshold swing: a simulation study. IEEE Trans Electron Devices 66:4425–4432

    Article  CAS  Google Scholar 

  28. Sentaurus TCAD (2018) Mountain view. User’s Manual, Synopsys, Inc., USA

    Google Scholar 

  29. Hurkx GAM, Klaassen DBM, Knuvers MPG (1992) A new recombination model for device simulation including tunneling. IEEE Trans Electron Devices 39:331–338

    Article  Google Scholar 

  30. Boucart K (2010) Simulation of double-gate silicon tunnel FETs with a high-k gate dielectric. Ph.D. dissertation, École Polytechnoique Fédérale de Lausanne, Switzerland

  31. Lee JS, Seo JH, Cho S et al (2013) Simulation study on effect of drain underlap in gate-all-around tunneling field-effect transistors. Curr Appl Phys 13:1143–1149

    Article  Google Scholar 

Download references

Acknowledgments

The authors are grateful to National Natural Science Foundation of China, Natural Science Foundation of Shang under Grant, Shanghai Science and Technology Innovation Action Plan and Science and Technology Commission of Shanghai Municipality for the financial support.

Funding

This work was supported in part by National Natural Science Foundation of China under Grant 61974056, in part by Natural Science Foundation of Shang under Grant 19ZR1471300, in part by Shanghai Science and Technology Innovation Action Plan under Grant 19511131900, and in part by Shanghai Science and Technology Explorer Plan under Grant 21TS1401700.

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Conceptualization, methodology, writing- original draft preparation: Xueke Wang; Data analysis: Xueke Wang and Yabin Sun; Writing- review and editing: Yun Liu and Xiaojin Li; Supervision: Ziyu Liu and Yanling Shi; Resources and funding acquisition: Ziyu Liu.

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Correspondence to Yabin Sun or Ziyu Liu.

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Wang, X., Sun, Y., Liu, Z. et al. Design Optimization of Nanotube Tunnel Field-Effect Transistor with Bias-Induced Electron-Hole Bilayer. Silicon 14, 9071–9082 (2022). https://doi.org/10.1007/s12633-022-01666-y

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