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An Improved Analytical Modeling and Simulation of Gate Stacked Linearly Graded Work Function Vertical TFET

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Abstract

In this paper, a 2D analytical potential model for n + SiGe Gate stacked linearly graded work function Vertical TFET (n + SiGe GS-LGW-VTFET) is developed with incorporating the effect of source and drain depletion region towards the channel. The proposed novel structure is developed from linearly graded for equalizing disruption of the work function having symmetric potential distribution effect on the device channel, which noticeably improve the device performance by reducing the short channel effect. The Poisson equation is solved in terms of channel surface potential and electric field using the parabolic approximation approach. This model also used some accurate analysis by employing the SiO2 and HfO2 with gate stacking method in order to increase the better gate control over the channel length. This model can initially forecast with the effect of gate-source voltage (Vgs) and drain-source voltage (Vds) thereafter gate oxide thickness, linearly graded work function, and SiGe mole fraction. The electric field is derived using the surface potential model, and thereafter, in order to extract the drain current characteristics, our suggested model accounts for the variables of the Kane model by integrating the band-to-band tunneling generation rate over the tunneling region. The proposed model efficiency has been confirmed by the drive characteristics of our model are in coincides nicely with that of simulation results.

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Acknowledgements

The authors are grateful to NIT, Jalandhar for their support during the research.

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The author(s) received no financial support for the research, authorship, and/or publication of this article.

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Contributions

Shailendra Singh: Validation and modeling, Writing and Editing, conceptualization, Simulation, TCAD Software, Writing- draft preparation, Investigation.

Shilpi Yadav: Methodology, Data curation, Visualization.

Sanjeev Kumar Bhalla: Supervision and revision.

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Correspondence to Shailendra Singh.

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Singh, S., Yadav, S. & Bhalla, S.K. An Improved Analytical Modeling and Simulation of Gate Stacked Linearly Graded Work Function Vertical TFET. Silicon 14, 4647–4660 (2022). https://doi.org/10.1007/s12633-021-01244-8

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